Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

• US 6,882,015 B2
• Filed: 09/12/2003
• Issued: 04/19/2005
• Est. Priority Date: 06/11/1999
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ning, Tak H., Cote, William J., Bernstein, Kerry, Bracchitta, John A., Pricer, Wilbur D.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US10/660,755
• Publication Number:
  US 20040046230A1
• Time in Patent Office: 585 Days
• Field of Search: 361/275.1, 257/379, 257/381, 324/522
• US Class Current: 257/379
• CPC Class Codes: H01G 4/1272 Semiconductive ceramic capacitors
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Claims

1. A circuit for monitoring a plurality of capacitor segments, the circuit comprising:

a charge monitoring circuit coupled to each capacitor segment;

a coupling circuit for selectively coupling and decoupling one of said capacitor segments from among a plurality of states; and

a control circuit for sequentially controlling said coupling circuit of each of said capacitor segments so as to disconnect a failed capacitor segment while said other capacitor segments are monitored.

2. The circuit of claim 1, wherein each of said capacitor segments comprises a plurality of plates and wherein said coupling circuit comprises at least one n-channel transistor connected between said control circuit and a plate of said capacitor segment.

3. The circuit of claim 2, further comprising a fuse circuit provided between said capacitor segment and said at least one n-channel transistor.

4. The circuit of claim 1, wherein each of said capacitor segments comprises a plurality of plates and wherein said coupling circuit comprises at least one p-channel transistor connected between said control circuit and a plate of said capacitor segment, the other plate of the capacitor segment being connected to a ground potential.

5. The circuit of claim 4, wherein said coupling circuit further comprises a fuse circuit connected between said control circuit and said at least one p-channel transistor.

6. The circuit of claim 1, wherein said charge monitoring circuit outputs a signal based on an amount of current flowing through said capacitor segment when said coupling segment is in a test state.

7. The circuit of claim 1, wherein said charge monitoring circuit comprises an integrator circuit.

8. The circuit of claim 1, wherein the control circuit controls the coupling circuit such that the capacitor segment is disconnected only after failing at least twice.

9. A circuit for monitoring a plurality of capacitor segments, each capacitor segment comprising a first low dielectric insulator layer, a low resistance conductor formed into at least two interdigitized patterns on a surface of said first low dielectric insulator layer and high dielectric material provided between said two interdigitized patterns, the circuit comprising:

a charge monitoring circuit coupled to each of said capacitor segments;

a coupling circuit connected to each of said capacitor segments, said coupling circuit selectively coupling and decoupling each capacitor segment to one of a disabled state, an enabled state and a testing state; and

a control circuit connected to said coupling circuit, said control circuit controlling said coupling circuit so as to place said coupling circuit of a failed capacitor in the disabled state while monitoring remaining ones of said plurality of capacitor segments.

10. The circuit of claim 9, wherein each of said capacitor segments comprises a plurality of plates and wherein said coupling circuit comprises at least one n-channel transistor connected between said control circuit and a plate of said capacitor segment.

11. The circuit of claim 10, further comprising a fuse circuit provided between said capacitor segment and said at least one n-channel transistor.

12. The circuit of claim 9, wherein each of said capacitor segments comprises a plurality of plates and wherein said coupling circuit comprises at least one p-channel transistor connected between said control circuit and a plate of said capacitor segment, the other plate of said capacitor segment being connected to a ground potential.

13. The circuit of claim 12, wherein the coupling circuit further comprises a fuse circuit connected between said control circuit and said at least one p-channel transistor.

14. The circuit of claim 9, wherein said charge monitoring circuit outputs a signal based on an amount of current flowing through said capacitor segment when said coupling segment is in the testing state.

15. The circuit of claim 9, wherein said charge monitoring circuit comprises an integrator circuit.

16. The circuit of claim 9, wherein the control circuit controls the coupling circuit such that the failed capacitor segment is placed in the disabled state only after failing at least twice in the testing state.