Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate

• US 6,882,030 B2
• Filed: 01/28/2002
• Issued: 04/19/2005
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Siniaguine, Oleg
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US10/059,898
• Publication Number:
  US 20020084513A1
• Time in Patent Office: 1,177 Days
• Field of Search: 257/621, 257/698, 257/735, 257/737, 257/690, 257/699, 257/685, 257/686, 257777-783, 438/106, 438/411, 438/461, 438/611, 438/667, 438/108, 438/109
• US Class Current: 257/621
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/814 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

To fabricate contacts on a wafer backside, openings (124) are formed in the face side of the wafer (104). A dielectric layer (140) and some contact material (150), e.g. metal, are deposited into the openings. Then the backside is etched until the contacts (150C) are exposed and protrude out. The protruding portion of each contact has an outer sidewall (150V). At least a portion of the sidewall is vertical or sloped outwards with respect to the opening when the contact is traced down. The contact is soldered to an another structure (410), e.g. a die or a PCB. The solder (420) reaches and at least partially covers the sidewall portion which is vertical or sloped outwards. The strength of the solder bond is improved as a result. The dielectric layer protrudes around each contact. The protruding portion (140P) of the dielectric becomes gradually thinner around each contact in the downward direction. The thinned dielectric is more flexible, and is less likely detach from the contact when the contact is pulled sideways. Other embodiments are also described.

Claims

1. A body comprising a semiconductor substrate which has a top surface and a bottom surface, wherein one or more through holes pass through the substrate between the top and bottom surfaces, the body comprising one or more circuit elements formed in and/or over the top surface of the semiconductor substrate;

a conductor formed in each through hole and protruding from the bottom surface of the semiconductor substrate, the conductor in each through hole being coupled to one or more of the circuit elements;

a dielectric separating the conductor in each through hole from the semiconductor substrate, wherein at each through hole the dielectric forms a protrusion on the bottom of the body around the conductor;

wherein at each through hole the conductor protrudes from the dielectric on the bottom of the body, the conductor thus having a protruding outer surface not covered by the dielectric, wherein at least a portion of the protruding outer surface is either vertical or sloped outwards, laterally away from the through hole, when the surface is traced down;

wherein throughout each protrusion formed by the dielectric, the dielectric becomes gradually thinner around the adjacent conductor as the protrusion is traced down.

2. An integrated circuit structure comprising:

a body comprising a semiconductor substrate which has a first surface and a second surface, wherein one or more through holes pass through the substrate between the first and second surfaces, the body comprising one or more circuit elements formed in and/or over the first surface of the semiconductor substrate;

a conductor formed in each through hole and protruding from a bottom surface of the semiconductor substrate, the conductor in each through hole being coupled to one or more of the circuit elements;

a dielectric separating the conductor in each through hole from the semiconductor substrate, wherein at each through hole the dielectric forms a protrusion on the bottom surface of the body around the conductor;

wherein throughout each protrusion formed by the dielectric, the dielectric becomes gradually thinner around the adjacent conductor as the protrusion is traced down.

3. The integrated circuit structure of claim 2 wherein at each through hole the conductor protrudes from the dielectric on the bottom surface of the body.

4. The integrated circuit structure of claim 2 in combination with a first substrate, wherein a protruding portion of each protruding conductor is attached to the first substrate.