Memory repeater

• US 6,882,082 B2
• Filed: 03/13/2001
• Issued: 04/19/2005
• Est. Priority Date: 03/13/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Greeff, Roy, Ovard, David
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/804,224
• Publication Number:
  US 20040225777A1
• Time in Patent Office: 1,498 Days
• Field of Search: 710/301, 710/307, 710/311, 710/316, 711/5, 711/100, 711/154, 365/223
• US Class Current: 310/307
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

A method and associated apparatus are provided for improving the performance of a high speed data bus, such as a memory bus, using selectively activated receiver and driver pairs. Each receiver and driver pair may be selectively activated to permit data communication on a segment of the high speed data bus coupled to the activated receiver and driver pair. Each receiver and driver pair may also be deactivated, thereby disconnecting at least a respective segment of the high speed data bus, so that communicating system components may be connected in a substantially stubless environment.

Claims

1. A data transfer interface, comprising:

a first receiver and driver pair coupled to a first segment of a first data bus, said first receiver and driver pair being configured to receive data on said first segment using said first receiver and selectively place data on said first segment using said first driver;

a second receiver and driver pair coupled to a second segment of said first data bus, said second receiver and driver pair being configured to receive data on said second segment using said second receiver and selectively place data on said second segment using said second driver; and

a selector circuit connected to said first and second receiver and driver pairs, said selector circuit selectively operating said first and second receiver and driver pairs according to a state of a command/address bus coupled to said selector circuit such that in a first state of said command/address bus said first receiver and driver pair passes data between said first bus segment and an I/O device and bypasses said second bus segment, and in a second state of said command/address bus said first and second receiver and driver pairs pass data between respective adjacent bus segments and bypass said I/O device

wherein said first and second segments of said first data bus is of a first data width and said I/O device is of a second data width, said first and second data widths being unequal.

2. An interface as in claim 1, wherein said I/O device comprises a memory device.

3. An interface as in claim 1, wherein said I/O device comprises a second data bus.

4. A data transfer interface, comprising:

a first receiver and driver pair coupled to a first segment of a first data bus, said first receiver and driver pair being connected to receive data on said first segment using said first receiver and selectively place data on said first segment using said first driver;

a second receiver and driver pair coupled to a second segment of said first data bus, said second receiver and driver pair being connected to receive data on said second segment using said second receiver and selectively place data on said second segment using said second driver;

a second data bus;

a device, coupled to said second data bus; and

an interface circuit coupled to a command/address bus, said first and second receiver and driver pairs, and said second data bus;

wherein

said interface circuit is configured, based on a state of said command/address bus, to receive data from said first receiver and selectively place said data for said device on said second data bus and receive data on said second data bus and selectively place said data on said first data bus, and

said first and second segments of said first data bus is of a first data width and said second data bus is of a second data width, said first and second data widths being unequal.

5. The interface of claim 4, wherein said first receiver and driver pair is coupled to said first segment via a first set of I/O pins, and said second receiver and driver pair is coupled to said second segment via a second set of I/O pins.

6. The interface of claim 4, wherein said interface circuit further comprises at least one of a multiplexer and demultiplexer that performs a data rate conversion between said first and second data buses.

7. The interface of claim 4, wherein said interface circuit further comprises a multiplexer and a demultiplexer which perform data rate conversions for data received on said first data bus that is placed on said second data bus and for data received on said second data bus that is placed on said first data bus.

8. The interface of claim 4, wherein said interface circuit further comprises at least one of a coder and decoder that performs at least one of a data encoding and decoding conversion between said first and second data buses.

9. The interface of claim 4, wherein said interface circuit further comprises a voltage converter that performs a voltage level conversion between said first and second data buses.

10. The interface of claim 4, wherein said second data bus is connected to at least one memory device.

11. The interface of claim 4, wherein said first data bus is connected to a memory controller.

12. The interface of claim 4, wherein said first data bus is connected to a processor.

13. The interface of claim 4, wherein said first data bus operates at a first data rate faster than a second data rate at which said second data bus operates.

14. The interface of claim 4, wherein said first data bus operates at a first voltage level less than a second voltage level at which said second data bus operates.

15. The interface of claim 4, wherein said first data bus transmits analog signals.

16. The interface of claim 4, wherein said first data bus transmits digital signals.

17. The interface of claim 4, wherein said first data bus transmits radio-frequency (RF) signals.

18. The interface of claim 4, wherein said first data bus is a substantially stubless data bus.

19. A memory module, comprising:

at least one memory device, each one of said at least one memory device being disposed on an integrated circuit, and comprising;

a memory; and

a data transfer interface connected to a first data bus and to said at least one memory device by a second data bus, said data transfer interface comprising;

a first receiver and driver pair coupled to a first segment of a first data bus, said first receiver and driver pair being connected to receive data on said first segment using said first receiver and selectively place data on said first segment using said first driver;

a second receiver and driver pair coupled to a second segment of said first data bus, said second receiver and driver pair being connected to receive data on said second segment using said second receiver and selectively place data on said second segment using said second driver; and

an interface circuit coupled to a command/address bus, said first and second receiver and driver pairs and a second data bus, wherein said interface circuit is configured, based on a state of said command/address bus, to receive data from said first receiver and selectively place said data for the memory on said second data bus, and receive data from the memory on said second data bus and selectively place said data on said first data bus;

wherein

said first and second segments of said first data bus is of a first data width and said second data bus is of a second data width, said first and second data widths being unequal; and

said second bus is coupled to said memory.

20. The memory module of claim 19, wherein said first receiver and driver pair is coupled to said first segment via a first set of I/O pins, and said second receiver and driver pair is coupled to said second segment via a second set of I/O pins.

21. The memory module of claim 19, wherein said interface circuit further comprises at least one of a multiplexer and demultiplexer that performs a data rate conversion between said first and second data buses.

22. The memory module of claim 19, wherein said interface circuit further comprises a multiplexer and a demultiplexer which perform data rate conversions for data received on said first data bus that is placed on said second data bus and for data received on said second data bus that is placed on said first data bus.

23. The memory module of claim 19, wherein said interface circuit further comprises at least one of a coder and decoder that performs at least one of a data encoding and decoding conversion between said first and second data buses.

24. The memory module of claim 19, wherein said interface circuit further comprises a voltage converter that performs a voltage level conversion between said first and second data buses.

25. The memory module of claim 19, wherein said first bus includes a first number of data paths and said second bus includes a second number of data paths, and said first number of data paths is less than said second number of data paths.

26. The memory module of claim 19, wherein said second data bus is connected to at least one memory device.

27. The memory module of claim 19, wherein said first data bus is connected to a memory controller.

28. The memory module of claim 19, wherein said first data bus is connected to a processor.

29. The memory module of claim 19, wherein said first data bus operates at a first data rate faster than a second data rate at which said second data bus operates.

30. The memory module of claim 19, wherein said first data bus operates at a first voltage level less than a second voltage level at which said second data bus operates.

31. The memory module of claim 19, wherein said first data bus transmits analog signals.

32. The memory module of claim 19, wherein said first data bus transmits digital signals.

33. The memory module of claim 19, wherein said first data bus transmits radio-frequency (RF) signals.

34. The memory module of claim 19, wherein said first data bus is a substantially stubless data bus.

35. A data exchange system, comprising:

a first data bus having at least first and second bus segments;

a controller connected to place data on and receive data from said first data bus;

a processor coupled to said controller, and

a data transfer interface, disposed on an integrated circuit and comprising;

a first receiver and driver pair coupled to a first segment of a first data bus, said first receiver and driver pair being connected to receive data on said first

segment using said first receiver and selectively place data on said first segment using said first driver;

a second receiver and driver pair coupled to a second segment of said first data bus, said second receiver and driver pair being connected to receive data on said second segment using said second receiver and selectively place data on said second segment using said second driver;

a second data bus;

a device, coupled to the second data bus; and

an interface circuit coupled to a command/address bus, said first and second receiver and driver pairs and a second data bus, wherein said interface circuit is configured, based on a state of said command/address bus, to receive data for the device on said first data bus and selectively place said data on said second data bus, and receive data from the device on said second data bus and selectively place said data on said first data bus;

wherein said first data bus is of a first data width, said second data bus is of a second data width, said first and second data widths being unequal.

36. A method of data communication comprising:

receiving data at first and second receivers coupled to respective first and second segments of a first data bus;

driving data using first and second drivers coupled to said respective first and second segments, said driving being performed according to a state of a command/address bus such that when said command/address bus is in a first state a first receiver and driver pair passes signals between said first segment of said first data bus and an I/O device and bypass said second segment, and when said command/address bus is in a second state said first and a second receiver and driver pairs pass signals between respective adjacent bus segments and bypass said I/O device;

wherein said first data bus is of a first data width, said I/O device is of a second data width, said first and second data widths being unequal.

37. A method as in claim 36, wherein said I/O device comprises a memory device.

38. A method as in claim 36, wherein said I/O device comprises a second data bus.

39. A method of data communication, comprising:

connecting an interface circuit having first and second receiver and driver pairs to respective first and second segments of a first data bus that operates at a first data rate;

connecting said interface circuit to at least one device on a second data bus that operates at a second data rate;

receiving and transmitting data on said first data bus using said first and second receiver and driver pairs;

receiving and transmitting data on said second data bus; and

based on a state of an command/address bus coupled to said interface circuit,

selectively placing data received from said first bus segment on said second bus segment when said command/address bus is in a first state;

selectively placing data received from said second bus segment on said first bus segment when said command/address bus is in a second state; and

selectively converting data received from one of said first and second data buses for use on the other of said first and second data buses;

wherein said first data bus is of a first data width, said second data bus is of a second data width, said first and second data widths being different.

40. A method as in claim 39, wherein said first data rate is faster than said second data rate.

41. A method as in claim 39, further comprising converting received data between said first data rate of said first data bus and said second data rate of said second data bus.

42. A method as in claim 39, further comprising converting received data between a first encoding of said first data bus and a second encoding of said second data bus.

43. A method as in claim 39, further comprising converting received data between a first voltage level of said first data bus to a second voltage level of said second data bus.

44. A method as in claim 43, wherein said first voltage level is less than said second voltage level.

45. A method as in claim 39, wherein devices of a first technology communicate with said interface circuit using said first data bus and devices of a second technology communicate with said interface circuit using said second data bus.

46. A method as in claim 45, wherein said devices of said first technology include at least one processor.

47. A method as in claim 45, wherein said devices of said second technology include at least one memory device.

48. A method as in claim 39, wherein said first data bus is a substantially stubless data bus.