Low power overdriven pass gate latch

• US 6,882,205 B2
• Filed: 11/08/2002
• Issued: 04/19/2005
• Est. Priority Date: 11/08/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Malley, Edward T., Curran, Brian W.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/290,636
• Publication Number:
  US 20040090257A1
• Time in Patent Office: 893 Days
• Field of Search: 327/172, 327/176, 327202-203, 327/208, 327210-212, 327214-215, 327218-219, 327291-293, 327/295, 327/386, 327/389, 361/91.1
• US Class Current: 327/291
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/32 Means for saving power

Abstract

A clocking circuit decreases the load on the local clock signals to save power. The load is decreased by altering the structure of the latches. Typically, a passgate style latch is used where both an NFET and a PFET are used to control dataflow. Here, the PFET has been removed and the load is decreased. However, it is difficult to pass a logical 1 through an NFET and this increases both the rising slew and rising edge delay through the latch. The effect is mitigated, though, by overdriving the local clock block (LCB) local clocks to drive a local clock to the latches by passgates using only NFET transistors in the master latches and slave latches. Overdrivig the NFET gate allows the NFET to pass a full-level logical 1 signal.

Claims

1. A clocking circuit for generating an overvoltage clock, comprising:

a global clock input,

a first inverter,

an intermediate clock node,

a second inverter,

a ground rail,

a first voltage rail,

a second voltage rail,

an overvoltage clock node,

wherein said global clock input is coupled to said first inverter, said first inverter is coupled to said ground rail, said first voltage rail and said intermediate clock node, and wherein said intermediate clock node is coupled to said second inverter, said second inverter is coupled to said ground rail, said second voltage rail and to said overvoltage clock node and said overvoltage clock node is coupled to a NFET pass gate latch circuit with an increasing voltage swing enabling said pass gate to pass a full level logical signal through said NFET pass gate latch circuit.

2. The clocking circuit according to claim 1 wherein said second inverter is comprised of

an NFET, and

a PFET,

wherein said NFET is coupled to said ground rail, and said PFET is coupled to said second voltage rail.

3. The clocking circuit according to claim 2 wherein said PFET has a high threshold voltage.

4. The clocking circuit according to claim 3 wherein said second voltage rail has a higher potential than said first voltage rail.

5. The clocking circuit according to claim 1 wherein said overvoltage clock node is coupled to said NFET pass-gate latch circuit comprising,

a latch data input,

an NFET pass gate, and

a pair of cross-coupled inverters.

6. The clock circuit according to claim 5 wherein the latch data input is coupled to said NFET pass gate, and said overvoltage clock node is also coupled to said NFET pass gate, while said NFET pass gate is coupled to said pair of cross-coupled inverters.

7. The clock circuit according to claim 6 wherein said pass-gate latch circuit controls dataflow and the effect of rising slew and rising edge delay through the pass-gate latch circuit is mitigated by overdriving the overgoltage clock node and using only NFET transistors in master and slave pass-gate latches whereby inncreasing the voltage swing allows the NFET of the pass-gate latch circuit to pass a full-level logical signal.

8. The clock circuit according to claim 7 wherein said overvoltage clock node is provided with a high voltage source (Vdd2>

Vdd) which is connected to the sources of the PFETs of the second inverter having a high voltage source connected to the sources of the second inverter'"'"'s PFET, and providing clock transitions from ground to the potential of the high voltage source, whereby clock transitions from ground to the potential of the high voltage source is distributed via wires to the pass-gate latches coupled to said overvoltage clock node.

9. The clock circuit according to claim 8 wherein said pass-gate latch circuit which buffers the latch data input.

10. The clock circuit according to claim 9 wherein there is provide slave latches coupled to an overvoltage clock node each are opened when said NFET pass gate is ON which allows the potential on a data input latch node to be ‘

passed’

via said NFET pass gate to a slave latch node, and when said slave latch node is at ground potential the NFET pass gate pulls slave latch node to ground, but when slave latch node is at Vdd potential the NFET pass gate could turn off prematurely, before slave latch node reaches Vdd potential, but such turnoff is avoided by selecting a high voltage source Vdd2 for the PFET of said second inverter.