Self-biasing for common gate amplifier

• US 6,882,224 B1
• Filed: 04/03/2003
• Issued: 04/19/2005
• Est. Priority Date: 04/03/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Groen, Eric D., Gaboury, Michael J.
• Primary Examiner(s): Nguyen, Khanh V.
• Application Number:
  US10/407,281
• Time in Patent Office: 747 Days
• Field of Search: 330/253, 330/257, 330/261, 330/263, 330/264, 330/285, 330/296
• US Class Current: 330/253
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/444 Diode used as protection means in an amplifier, e.g. as a limiter or as a switch
• CPC Class Codes: H03F 2200/72 the amplifier stage being a common gate configuration MOSFET
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03K 5/023 using field effect transistors
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

A data receiver having a transfer function that exhibits peaking at high frequencies is provided to compensate an input signal provided on a transmission channel having a low pass transfer function. The data receiver includes first and second differential input terminals, which receive the differential input signal from the transmission channel. The first differential input terminal is coupled to the source of a first common gate transistor in a first self-biased common gate amplifier. The second differential input terminal is coupled to the source of a second common gate transistor in a second self-biased common gate amplifier. A differential output signal is provided from the drain terminals of the first and second common gate transistors. The first and second differential input terminals are not directly connected to any transistor gates in the data receiver, thereby enabling these differential input terminals to be safely connected directly to the transmission channel.

Claims

1. A data receiver comprising:

a first input terminal configured to receive a first input signal from a transmission channel having a low pass transfer function;

a first self-biased common gate amplifier coupled to the first input terminal; and

a first output terminal coupled to the first self-biased common gate amplifier;

a second input terminal configured to receive an input signal from the transmission channel, wherein the first input signal and the second input signal form a differential input signal;

a second self-biased common gate amplifier coupled to the second input terminal; and

a second output terminal coupled to the second self-biased common oate amplifier, wherein the first and second output terminals are configured to provide a differential output signal;

a first input pad coupled to the first input terminal, wherein the first input pad is directly connected to the first self-biased common gate amplifier; and

a second input pad coupled to the second input terminal, wherein the second input pad is directly connected to the second self-biased common date amplifier, and wherein the first and second input pads are configured to receive the differential input signal from the transmission channel.

2. The data receiver of claim 1, further comprising a electrostatic discharge (ESD) circuit coupled to the first and second input terminals.

3. The data receiver of claim 2, wherein the ESD circuit comprises:

a first set of diode elements connected between the first input terminal and a plurality of supply voltage terminals; and

a second set of diode elements connected between the second input terminal and a plurality of supply voltage terminals.

4. The data receiver of claim 1, further comprising a bias circuit coupled to the first and second self-biased common gate amplifiers, wherein the bias circuit is configured to control currents flowing through the first and second self-biased common gate amplifiers.

5. The data receiver of claim 1, wherein the first self-biased common gate amplifier includes a first common gate transistor having a source coupled to the first input terminal and a drain coupled to the first output terminal, and wherein the second self-biased common gate amplifier includes a second common gate transistor having a source coupled to the second input terminal and a drain coupled to the second output terminal.

6. The data receiver of claim 5, further comprising a resistor connected between the source of the first common gate transistor and the source of the second common gate transistor.

7. The data receiver of claim 5, further comprising a variable bias circuit coupled to the first and second self-biased common gate amplifiers, wherein the variable bias circuit is configured to control currents flowing through the first and second common gate transistors, thereby controlling the transconductances of the first and second common gate transistors.

8. The data receiver of claim 5, wherein the first self-biased common gate amplifier further comprises:

a first resistor coupled between the drain of the first common gate transistor and a first voltage supply terminal;

a first capacitor coupled between the gate of the first common gate transistor and the first voltage supply terminal;

a first transistor having a drain and a gate coupled to the gate of the first common gate transistor; and

a second resistor coupled between the drain of the first transistor and the first voltage supply terminal;

and wherein the second self-biased common gate amplifier further comprises;

a third resistor coupled between the drain of the second common gate transistor and the first voltage supply terminal;

a second capacitor coupled between the gate of the second common gate transistor and the first voltage supply terminal;

a second transistor having a drain and a gate coupled to the gate of the second common gate transistor; and

a fourth resistor coupled between the drain of the second transistor and the first voltage supply terminal.

9. The data receiver of claim 8, wherein the first and second capacitors are variable-capacitance capacitors, whereby the capacitances of the first and second capacitors can be selected from a plurality of capacitances.

10. The data receiver of claim 9, wherein the second and fourth resistors are variable-resistance resistors, whereby the resistances of the second and fourth resistors can be selected from a plurality of resistances.

11. The data receiver of claim 8, wherein the second and fourth resistors are variable-resistance resistors, whereby the resistances of the second and fourth resistors can be selected from a plurality of resistances.

12. The data receiver of claim 8, further comprising:

a first bias transistor coupled between the source of the first common gate transistor and a second voltage supply terminal;

a second bias transistor coupled between the source of the first transistor and the second voltage supply terminal;

a third bias transistor coupled between the source of the second common gate transistor and the second voltage supply terminal; and

a fourth bias transistor coupled between the source of the second transistor and the second voltage supply terminal.

13. The data receiver of claim 12, further comprising:

a fifth resistor coupled between the sources of the first common gate transistor and the first transistor;

a sixth resistor coupled between the sources of the second common gate transistor and the second transistor; and

a seventh resistor coupled between the sources of the first and second common gate transistors.

14. The data receiver of claim 1, wherein the first and second self-biased common gate amplifiers are configured to have a transfer function that exhibits peaking at high frequencies, thereby compensating for the low pass transfer function of the transmission channel.

15. The data receiver of claim 1, wherein the first self-biased common gate amplifier is configured to have a transfer function that exhibits peaking at high frequencies, thereby compensating for the low pass transfer function of the transmission channel.

16. A data receiver comprising:

a first input terminal configured to receive a first input signal from a transmission channel having a low pass transfer function;

a first self-biased common gate amplifier coupled to the first input terminal; and

a first output terminal coupled to the first self-biased common gate amplifier; and

wherein the first self-biased common gate amplifier includes a first common gate transistor having a source coupled to the first input terminal and a drain coupled to the first output terminal.

17. The data receiver of claim 16, further comprising a variable bias circuit coupled to the first self-biased common gate amplifier, wherein the variable bias circuit is configured to control current flowing through the first common gate transistor, thereby controlling the transconductance of the first common gate transistor.

18. The data receiver of claim 16, wherein the first self-biased common gate amplifier further comprises:

a first resistor coupled between the drain of the first common gate transistor and a first voltage supply terminal;

a capacitor coupled between the gate of the first common gate transistor and the first voltage supply terminal;

a first transistor having a drain and a gate coupled to the gate of the first common gate transistor; and

a second resistor coupled between the drain of the first transistor and the first voltage supply terminal.

19. The data receiver of claim 18, wherein the capacitor is a variable-capacitance capacitor, whereby the capacitance of the capacitor can be selected from a plurality of capacitances.

20. The data receiver of claim 19, wherein the second resistor is a variable-resistance resistor, whereby the resistance of the second resistor can be selected from a plurality of resistances.

21. The data receiver of claim 18, wherein the second resistor is a variable-resistance resistor, whereby the resistance of the second resistor can be selected from a plurality of resistances.

22. The data receiver of claim 18, further comprising:

a first bias transistor coupled between the source of the first common gate transistor and a second voltage supply terminal; and

a second bias transistor coupled between the source of the first transistor and the second voltage supply terminal.

23. The data receiver of claim 22, further comprising a third resistor coupled between the sources of the first common gate transistor and the first transistor.

24. A method of processing an input signal comprising:

transmitting a first input signal on a transmission channel having a low pass transfer function; and

receiving the first input signal with a first self-biased common-gate amplifier having a transfer function that exhibits peaking at high frequencies, thereby compensating for the low pass transfer function of the transmission channel.

25. The method of claim 24, further comprising programming the transfer function of the first self-biased common-gate amplifier in response to the low pass transfer function of the transmission channel.

26. The method of claim 25, wherein the step of programming the transfer function comprises selecting the resistance of a variable-resistance resistor in the first self-biased common-gate amplifier.

27. The method of claim 26, wherein the step of programming the transfer function comprises selecting the capacitance of a variable-capacitance capacitor in the first self-biased common-gate amplifier.

28. The method of claim 25, wherein the step of programming the transfer function comprises selecting the capacitance of a variable-capacitance capacitor in the first self-biased common-gate amplifier.

29. The method of claim 24, wherein the first self-biased common gate amplifier includes a first common gate transistor, the method further comprising biasing the first common gate transistor, such that a bias current flows through the first common gate transistor.

30. The method of claim 29, further comprising selecting the bias current such that the first common gate transistor exhibits a predetermined termination resistance.

31. The method of claim 24, further comprising:

transmitting a second input signal on the transmission channel, wherein the first input signal and the second input signal form a differential input signal; and

receiving the second input signal with a second self-biased common-gate amplifier, wherein the second self-biased common-gate amplifier is coupled to the first self-biased common-gate amplifier to form a differential self-biased common-gate amplifier having a transfer function that exhibits peaking at high frequencies, thereby compensating for the low pass transfer function of the transmission channel.

32. The method of claim 31, further comprising programming the transfer function of the differential self-biased common-gate amplifier in response to the low pass transfer function of the transmission channel.

33. The method of claim 32, wherein the step of programming the transfer function comprises selecting the resistance of variable-resistance resistors in the first and second self-biased common-gate amplifier.

34. The method of claim 33, wherein the step of programming the transfer function comprises selecting the capacitance of variable-capacitance capacitors in the first and second self-biased common-gate amplifier.

35. The method of claim 32, wherein the step of programming the transfer function comprises selecting the capacitance of variable-capacitance capacitors in the first and second self-biased common-gate amplifier.

36. The method of claim 31, wherein the first self-biased common gate amplifier includes a first common gate transistor and the second self-biased common gate amplifier includes a second common gate transistor, the method further comprising:

biasing the first common gate transistor, such that a first bias current flows through the first common gate transistor; and

biasing the second common gate transistor, such that a second bias current flows through the second common gate transistor.

37. The method of claim 36, further comprising selecting the first and second bias currents such that the first and second common gate transistors exhibit predetermined termination resistances.

38. A data receiver comprising:

first and second input pads configured to receive a differential input signal from a transmission channel having a low pass transfer function;

a electrostatic discharge (ESD) circuit coupled to the first and second input pads; and

a differential amplifier, comprising a transistor having a source and a drain, the ESD circuit connected to the source or the drain.

39. The data receiver of claim 38, wherein the ESD circuit comprises:

a first set of diode elements connected between the first input pad and a plurality of supply voltage terminals; and

a second set of diode elements connected between the second input pad and a plurality of supply voltage terminals.

40. The data receiver of claim 38, wherein the differential amplifier further comprises a self-biased common gate amplifier comprising the transistor.

41. A data receiver comprising:

an input terminal configured to receive an input signal from a transmission channel having a low pass transfer function;

a self-biased common gate amplifier coupled to the input terminal; and

an output terminal coupled to the self-biased common gate amplifier;

wherein the self-biased common gate amplifier is self-biased at some low and some high frequencies, and wherein the self-biased common gate amplifier includes a common gate transistor having a source coupled to the input terminal and a drain coupled to the output terminal.