Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges

• US 6,882,572 B2
• Filed: 05/19/2004
• Issued: 04/19/2005
• Est. Priority Date: 12/27/2001
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Yeh, Bing, Wang, Chih Hsin
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/849,975
• Publication Number:
  US 20040212009A1
• Time in Patent Office: 335 Days
• Field of Search: 365/185.05, 365/185.14, 365/185.18, 365/185.26, 365/185.28, 257/315, 257/316, 257/317
• US Class Current: 365/185.18
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench. An electrically conductive floating gate is formed over and insulated from a portion of the channel region, with a horizontally oriented edge extending therefrom. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion disposed adjacent to and insulated from the floating gate edge.

Claims

1. A method of operating an electrically programmable and erasable memory device having an electrically conductive floating gate disposed over and insulated from a substrate of semiconductor material, and an electrically conductive control gate having at least a portion thereof disposed laterally adjacent to the floating gate and insulated therefrom by an insulating material, the method comprising the step of:

placing a voltage on the control gate that is sufficiently positive relative to a voltage of the floating gate to induce electrons on the floating gate to laterally tunnel from a horizontally oriented edge extending from a lateral side of the floating gate, through the insulating material, and onto the control gate via Fowler-Nordheim tunneling.

2. The method of claim 1, further comprising the steps of:

placing a positive voltage on a source region of the substrate formed at least partially underneath and insulated from the floating gate to capacitively couple the positive voltage onto the floating gate;

placing a positive voltage on a drain region of the substrate that is disposed underneath a trench formed in the surface of the substrate; and

placing a positive voltage on the control gate which has a first portion extending down into the trench and a second portion disposed laterally adjacent to the floating gate edge;

wherein electrons are induced to travel from the drain region, generally along a sidewall of the trench and onto the floating gate.

3. A method of operating an electrically programmable and erasable non-volatile memory cell having a first and a second state, and including an electrically conductive floating gate disposed over and insulated from a substrate of semiconductor material, and an electrically conductive control gate having at least a portion thereof disposed laterally adjacent to the floating gate, the method comprising the steps of:

establishing a first state of the memory cell by injecting electrons from a drain region of the substrate onto the floating gate, wherein the source region is disposed below a surface of the substrate and the injected electrons travel through the substrate in a direction generally perpendicular to the surface of the substrate; and

establishing a second state of the memory cell by removing electrons from the floating gate to the control gate via Fowler-Nordheim tunneling through an insulating material disposed therebetween, wherein the removed electrons tunnel from a horizontally oriented edge extending from a lateral side of the floating date, through the insulating material, and onto the control gate in a direction generally parallel to the surface of the substrate.