Method for operating a semiconductor memory, and semiconductor memory

• US 6,882,584 B2
• Filed: 12/12/2002
• Issued: 04/19/2005
• Est. Priority Date: 12/12/2001
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Perner, Martin
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/317,972
• Publication Number:
  US 20030107942A1
• Time in Patent Office: 859 Days
• Field of Search: 365/200, 365/230.03, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory and a method for operating the semiconductor memory store information items at least in triplicate at memory addresses in a plurality of memory areas, preferably memory banks, and read the information items therefrom. A checking unit contains synchronization circuits compares the data values that are read and, if the information items that are read differ, can ascertain and possibly immediately correct storage errors. The method of operating the memory enables quasi-random access to memory cells using a permutation circuit. In a test mode for the semiconductor memory, an error log circuit can output error log data instead of or in addition to data values that are read.

Claims

1. A method for operating a semiconductor memory having at least three memory areas each including a plurality of memory addresses, which comprises:

connecting the memory addresses from the at least three memory areas in parallel with one another to form a group of memory addresses having a respective memory address from each of the at least three memory areas;

writing a given information item to all of said memory addresses in said group;

reading the information items from each of said memory addresses in said group; and

performing an error check on the information items by checking if the information items read from said memory addresses in said group are identical to one another.

2. The method according to claim 1, wherein the memory areas are memory banks.

3. The method according to claim 2, wherein the memory addresses from precisely four memory banks connected in parallel with one another.

4. The method according to claim 1, which further comprises, if the error check reveals that the information items at the memory addresses in the group are not identical to one another, calculating a most-commonly occurring data value in the memory addresses of the group, and correcting the memory addresses by writing the most-commonly occurring data value to all of the memory addresses in the group.

5. The method according to claim 4, wherein the correcting step is performed automatically upon reading the memory addresses in the block.

6. The method according to claim 4, wherein the correcting step is performed automatically upon refreshing the memory areas.

7. The method according to claim 1, which further comprises operating the semiconductor memory in a test mode by repeatedly writing information items to various groups of the memory addresses in a given order and reading from the various groups of the memory addresses successively in a different order.

8. The method according to claim 7, which further comprises permitting the given order for all the various groups of memory addresses to provide the different order for reading the various groups of memory addresses successively.

9. The method according to claim 8, which further comprises permuting differently by choosing a different permutation when reading information items than when writing information items.

10. The method according to claim 8, which further comprises permuting the given order for the group of memory addresses by permuting the row addresses and the column addresses independently of one another.

11. The method according to claim 8, which further comprises permuting the order for the various groups of memory addresses accessed successively by logically combining each of the memory addresses, digit by digit, with a permutation constant having as many binary digits as memory addresses in the given one of the memory areas, in binary notation by using an arithmetic operation to give a digit sequence indicating the permutated memory address, the arithmetic operation logically combining two bit values to give a logic value “

1”

at a precise point of differing bit values.

12. The method according to claim 7, which further comprises:

permuting the various groups of the memory addresses among one another when writing and reading with permutation constants; and

altering the information items to be stored and read again using the permutation constants.

13. The method according to claim 7, which further comprises:

providing a circuit on the semiconductor memory; and

permuting the given order of successively accessing various groups of memory addresses with the circuit on the semiconductor memory.

14. The method according to claim 1, which further comprises operating the semiconductor memory in a test mode by reading the information items while creating an error log based on the error check being output instead of the information items being read.

15. The method according to claim 14, wherein the reading of information items from a group of the memory addresses involves outputting a data value to indicate when the information items being read are identical to one another.

16. The method according to claim 15, which further comprises:

outputting just the data value with no indication of the memory addresses; and

using the data value for error counting.

17. The method according to claim 15, which further comprises:

organizing the memory addresses of respective memory areas into a plurality of groups;

providing a databus having a respective data line connected to each of the groups;

simultaneously accessing the information items in the plurality of groups of memory addresses with the data bus; and

outputting the data value from each group of memory addresses that each data line in the data bus is accessing.

18. The method according to claim 17, which further comprises:

creating an error log when the information items have been read and the data lines successively output over a plurality of time cycles; and

storing error log details in the error log about error occurrences, types of errors, numbers of data lines outputting an error, and the memory addresses that have been read from.

19. A semiconductor memory, comprising:

at least three memory areas each having a multiplicity of memory addresses for storing information items;

synchronization circuits for connecting memory addresses from said at least three memory areas in parallel with one another to form a group and to allow each read and write operation to access said group of memory addresses and for routing a given information item to all of said memory addresses in said group during a write operation; and

a checking unit for checking if said information items at said memory addresses in said group are identical to one another.

20. The semiconductor memory according to claim 19, wherein said synchronization circuits are integrated in said checking unit.

21. The semiconductor memory according to claim 19, wherein each of said synchronization circuits is connected to a respective one of said memory addresses from each of said memory areas.

22. The semiconductor memory according to claim 19, wherein said memory areas are memory banks.

23. The semiconductor memory according to claim 19, wherein each of said synchronization circuits has a correction circuit routing a standard data value to all the memory addresses connected to said respective synchronization circuit following at least of reading and refreshing of the information items.

24. The semiconductor memory according to claim 23, wherein:

said synchronization circuits and said correction circuits are activated in a first operating mode;

just said synchronization circuits are activated in a second operating mode; and

said synchronization circuits and said correction circuits are deactivated in a third operating mode;

only one of said operating modes being selectable at a given time.

25. The semiconductor memory according to claim 19, further comprising a circuit interchanging memory addresses within one of said memory areas and redirecting commands to the interchanged memory addresses.

26. The semiconductor memory according to claim 19, further comprising a circuit for outputting an error log, said circuit outputting data values indicating if the information items read in said group of said memory addresses are identical to one another.

27. The semiconductor memory according to claim 26, wherein said circuit outputs said error log instead of the information items read from said memory addresses.

28. The semiconductor memory according to claim 26, wherein said circuit outputs said error log in addition to the information items read from said memory addresses.

29. The semiconductor memory according to claim 26, wherein:

said memory addresses individually output just the information items read from the individual memory addresses in said group while in a first operating mode;

said memory addresses individually output just the data values, instead of the information items, and indicate if the information items are identical to one another, while in a second operating mode; and

said memory addresses individually output the data values and additionally the information items being read, while in a third operating mode;

only one of said operating modes being selectable at a time.