Method and apparatus for input rate regulation associated with a packet processing pipeline
First Claim
1. An apparatus, comprising:
- a pipeline having a series of stages, one of said pipeline stages having a content addressable memory interface for coupling to a content addressable memory that stores a pointer to input flow information for a packet, said pointer to said input flow information obtainable from said content addressable memory with information from said packet'"'"'s header, another of said pipeline stages having a first interface that receives information indicative of said packet'"'"'s size and a second interface that receives said input flow information, said input flow information comprising a pointer to information describing an input bucket for said packet, said other pipeline stage further comprising a register to store said input bucket information and policing logic coupled to both said first interface and said register.
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Accused Products
Abstract
A method is described that involves presenting packet header information from a packet and packet size information for the packet to a pipeline that comprises multiple stages. One of the stages identifies, with the packet header information, where input flow information for the packet is located. The input flow information is then fetched. The input flow information identifies where input capacity information for the packet is located and the input capacity information is then fetched. Another of the stages compares an input capacity for the packet with the packet'"'"'s size and indicates whether the packet is conforming or non-conforming based upon the comparison. The input capacity is calculated from the input capacity information.
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Citations
48 Claims
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1. An apparatus, comprising:
a pipeline having a series of stages, one of said pipeline stages having a content addressable memory interface for coupling to a content addressable memory that stores a pointer to input flow information for a packet, said pointer to said input flow information obtainable from said content addressable memory with information from said packet'"'"'s header, another of said pipeline stages having a first interface that receives information indicative of said packet'"'"'s size and a second interface that receives said input flow information, said input flow information comprising a pointer to information describing an input bucket for said packet, said other pipeline stage further comprising a register to store said input bucket information and policing logic coupled to both said first interface and said register. - View Dependent Claims (2, 3, 4, 5)
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6. A method comprising:
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a) presenting packet header information from a packet and packet size information for said packet to a pipeline that comprises multiple stages;
b) identifying at one of said stages, with said packet header information, where input flow information for said packet is located;
c) fetching said input flow information, said input flow information identifying where input capacity information for said packet is located;
d) fetching said input capacity information;
e) comparing, within another of said stages, an input capacity for said packet with said packet'"'"'s size and indicating whether said packet is conforming or non-conforming based upon said comparison, said input capacity calculated from said input capacity information. - View Dependent Claims (7, 8, 9, 10)
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11. An apparatus for regulating traffic offered to a network by a first user of said network and a second user of said network, said apparatus comprising:
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a) a first pipeline stage that operates to retrieve, in response to a first packet being sent from said first user to said network, a first input flow identifier that points to a first memory location where a first input flow is located, said first input flow allocated to said first user, said first input flow having a first input rate; and
,b) a second pipeline stage that;
i) operates to retrieve one or more parameters that describe said first input rate so that it can be determined if said sending of said first packet conforms to said first input rate ii) while said first pipeline stage operates to retrieve a second input flow identifier that points to a second memory location where a second input flow is located, said second input flow allocated to said second user, said second input flow having a second input rate, said retrieving of a second input flow identifier in response to a second packet being sent from said second user to said network. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method for regulating traffic offered to a network by a first user of said network and a second user of said network, said method comprising:
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a) using a first pipeline stage to retrieve, in response to a first packet being sent from said first user to said network, a first input flow identifier that points to a first memory location where a first input flow is located, said first input flow allocated to said first user, said first input flow having a first input rate; and
b) using a second pipeline stage to retrieve one or more parameters that describe said first input rate so that it can be determined if said sending of said first packet conforms to said first input rate while using said first pipeline state to retrieve a second input flow identifier that points to a second memory location where a second input flow is located, said second input flow allocated to said second user, said second input flow having a second input rate, said retrieving of a second input flow identifier in response to a second packet being sent from said second user to said network. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. An apparatus for regulating traffic offered to a network by a first user of said network and a second user of said network, said apparatus comprising:
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a) a first pipeline stage coupled to a first memory, said first memory to provide to said first pipeline stage;
(i) during a first pipeline cycle;
a first input flow identifier;
(ii) during a second pipeline cycle;
a second input flow identifier; and
b) a second pipeline stage that follows said first pipeline stage, said second pipeline stage comprising;
1) a data bus to receive from a second memory;
(i) during said second pipeline cycle and from a location of said second memory pointed to by a first output flow identifier;
parameters belonging to said first input flow;
(ii) during a third pipeline cycle and from a location of said second memory pointed to by said second output flow identifier;
parameters belonging to said second input flow;
2) register space in which to store;
(iii) during said second pipeline cycle;
parameters from which a first amount of data can be calculated, said first packet being in conformance with said first input flow'"'"'s input rate if said first packet'"'"'s size is not greater than said first amount of data;
(iv) during said third pipeline cycle;
parameters from which a second amount of data can be calculated, said second packet being in conformance with said second input flow'"'"'s input rate if said second packet'"'"'s size is not greater than said second amount of data;
3) logic circuitry to determine;
(v) during said second pipeline cycle;
if said first packet is in conformance with said first input flow'"'"'s input rate;
(vi) during said third pipeline cycle;
if said first packet is in conformance with said first input flow'"'"'s input rate. - View Dependent Claims (42, 43)
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44. A method, comprising:
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a) during a first pipeline cycle;
with a first pipeline stage;
identifying a memory location where input flow information for a packett can be found, said packet sent from a user of a network to said network;
with a second pipeline stage that follows said first pipeline stage;
identifying a memory location where output flow information for a second packet can be found, said second packet to exit said network so that it can be received by a second user of said network;
b) during a second pipeline cycle that follows said first pipeline cycle;
with a third pipeline stage that follows said first pipeline stage but precedes said second pipeline stage;
fetching said input flow information and determining if said first packet conforms to said input flow'"'"'s input rate;
with a fourth pipeline stage that follows said second pipeline stage;
fetching said output flow information and calculating a delay for said second packet that conforms to said output flow'"'"'s output rate. - View Dependent Claims (45)
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46. A machine readable medium containing a description of a semiconductor circuit design for regulating traffic offered to a network by a first user of said network and a second user of said network, said description comprising a description of:
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a) a first pipeline stage to lookup a first input flow identifier, where, said first input flow identifier points to a first memory location where parameters for a first input flow are located, where said first input flow is for a first packet that is sent from said first user and stored into a packet buffer, and where, said first input flow is characterized at least by a first input rate; and
,b) a second pipeline stage having policing logic circuitry coupled to register storage space, said register storage space to provide to said policing logic circuitry a characteristic of said first input rate, said second pipeline stage to;
(i) determine whether said first packet conforms to said first output rate, (ii) during a same pipeline cycle in which said first pipeline stage looks up a second input flow identifier that points to a second memory location where parameters for a second input flow are located, where, said second input flow is for a second packet that is sent from said second user and stored into said packet buffer, and where, said second input flow is characterized at least by a second output rate. - View Dependent Claims (47, 48)
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Specification