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Method and apparatus for input rate regulation associated with a packet processing pipeline

  • US 6,882,642 B1
  • Filed: 10/14/1999
  • Issued: 04/19/2005
  • Est. Priority Date: 10/14/1999
  • Status: Expired due to Fees
First Claim
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1. An apparatus, comprising:

  • a pipeline having a series of stages, one of said pipeline stages having a content addressable memory interface for coupling to a content addressable memory that stores a pointer to input flow information for a packet, said pointer to said input flow information obtainable from said content addressable memory with information from said packet'"'"'s header, another of said pipeline stages having a first interface that receives information indicative of said packet'"'"'s size and a second interface that receives said input flow information, said input flow information comprising a pointer to information describing an input bucket for said packet, said other pipeline stage further comprising a register to store said input bucket information and policing logic coupled to both said first interface and said register.

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