Method and apparatus for translating detected wafer defect coordinates to reticle coordinates using CAD data

• US 6,882,745 B2
• Filed: 12/19/2002
• Issued: 04/19/2005
• Est. Priority Date: 12/19/2002
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Schraub, David M., Brankner, Keith
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US10/324,261
• Publication Number:
  US 20040121496A1
• Time in Patent Office: 852 Days
• Field of Search: 250/307, 382/144
• US Class Current: 382/144
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

Systems and methods are described for translating detected wafer defect coordinates to reticle coordinates using CAD data. A wafer inspection image is provided and coordinates of potential defects in the wafer are determined. Then the wafer inspection image is converted into a predetermined image format. CAD data for the device under test is then used to produce a second image, also in the predetermined image format. The CAD-derived image and the wafer-derived image are then aligned, and the coordinates of potential defects in the wafer are converted into CAD coordinates. The CAD coordinates are then used to navigate through the reticle for the wafer in order to locate reticle defects corresponding to the detected wafer defects.

Claims

1. A method of locating repeater defects in a device under test, comprising:

providing an inspection image of a device under test including detected coordinates of potential repeater defects;

converting the inspection image into a first image in a predetermined image format;

providing CAD data for the device under test;

converting the CAD data into a second image in the predetermined image format;

aligning the first and second images;

converting the detected coordinates of potential repeater defects into CAD coordinates; and

locating repeater defects as a function of the CAD coordinates.

2. The method of claim 1, the device under test comprising a wafer.

3. The method of claim 1, the device under test comprising a die of a wafer.

4. The method of claim 1, further comprising, locating repeater defects in a reticle for the device under test, as a function of the CAD coordinates.

5. The method of claim 1, the step of converting the CAD data into the second image comprising, performing a lithography modeling step.

6. The method of claim 1, the detected coordinates of potential repeater defects comprising a repeater defect file.

7. The method of claim 6, the step of converting the detected coordinates into CAD coordinates comprising, mapping the repeater defect file to CAD coordinates to produce a tagged data file.

8. The method of claim 7, the repeater defect file comprising wafer stage coordinates.

9. A method for locating repeater defects in a semiconductor wafer reticle, comprising:

generating a wafer image of a semiconductor wafer under test;

determining stage coordinates for detected potential repeater defects in the wafer under test;

generating a CAD image from CAD data related to the semiconductor wafer under test;

aligning the wafer image and the CAD image and determining CAD coordinates from the stage coordinates corresponding to said potential repeater defects; and

locating repeater defects in a semiconductor wafer reticle for the semiconductor wafer under test as a function of the CAD coordinates.

10. The method of claim 9, the step of generating a CAD image comprising, conditioning said CAD data using lithography modeling.

11. The method of claim 9 further comprising, storing CAD coordinates corresponding to said potential repeater defects in a repeater defect file.

12. The method of claim 11 further comprising, mapping the repeater defect file to CAD coordinates to produce a tagged data file.

13. A method of locating repeater defects in a device under test, comprising:

mounting a device under test on a stage;

generating an image of the device under test;

determining stage coordinates for detected potential repeater defects in the device under test;

generating a CAD image from CAD data corresponding to the device under test;

converting the image of the device under test and the CAD image into a common image format;

aligning the image of the device under test and the CAD image in the common image format;

determining CAD coordinates of the potential repeater defects from the stage coordinates for the detected potential repeater defects; and

locating repeater defects as a function of the CAD coordinates.

14. The method of claim 13, the device under test comprising a wafer.

15. The method of claim 14 further comprising, locating repeater defects in a reticle of the wafer as a function of the CAD coordinates.