Cache control device and method with TLB search before key receipt

• US 6,883,077 B2
• Filed: 02/27/2002
• Issued: 04/19/2005
• Est. Priority Date: 10/25/2001
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kimura, Hiroaki, Yamazaki, Iwao, Shirahige, Yuji
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US10/083,161
• Publication Number:
  US 20030084254A1
• Time in Patent Office: 1,147 Days
• Field of Search: 711/3, 711/113, 711/145, 711/152, 711/163, 711/164, 711/203, 711/204, 711/205, 711/206, 711/207, 711/213, 712/239, 713/200, 713/202
• US Class Current: 711/164
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1466 Key-lock mechanism

Abstract

In an information processsing unit with key controlled protection, since it takes a long time to fetch a storage key from key storage, an instruction and computation unit of a CPU receives data from a memory control unit of the CPU before a key is received, and then the transferred storage key is checked.

Claims

1. An apparatus for controlling a cache memory that stores data, said apparatus provided with protection via a storage key to permit access to data stored in the cache, said apparatus comprising:

a translation lookaside buffer device registering a correspondence relation between a logical address and a physical address;

an address translation device transforming a logical address of the access into a physical address when the logical address of the access is not registered in the translation lookaside buffer device;

a requesting device that requests the storage key;

a control device that registers a translation result of the logical address of the access in the translation lookaside buffer device and initiates a search of the translation lookaside buffer device and a retrieval of the data in the cache without waiting for the requested storage key to be received, thereby enables a search of the translation lookaside buffer device for a successive data access without waiting for the requested storage key to be received; and

a transfer device that transmits the data retrieved from the cache.

2. The apparatus according to claim 1, wherein the transfer device transmits the retrieved data without waiting for arrival of the demanded storage key.

3. The apparatus according to claim 1, further comprising:

a translation lookaside buffer device registering a correspondence relation between a logical address and a physical address; and

an address translation device transforming the logical address into the physical address, wherein

when a logical address of the access is not registered in the translation lookaside buffer device, the control device demands translation of the logical address of the access from the address translation device, registers the translation result of the logical address of the access in the translation lookaside buffer device, and releases the address translation device without waiting for arrival of the demanded storage key.

4. The apparatus according to claim 3, further comprising a plurality of key access ports storing an arrived storage key, wherein the address translation device translates a plurality of logical addresses associated with a plurality of accesses, and the demand device demands a corresponding storage key each time translation completes.

5. The apparatus according to claim 1, wherein the control device completes an access process for an access that does not require the key control protection, without waiting for arrival of the demanded storage key.

6. An apparatus as recited in claim 1, wherein the transfer device transfers the data retrieved from the cache to an instruction processor without waiting for arrival of the requested storage key.

7. A cache control method used for a data processing device provided with key control protection using a storage key for an access to data, comprising:

searching a translation lookaside buffer for a logical address of the access;

transforming the logical address of the access into a physical address when the logical address of the access is not registered in the translation lookaside buffer device;

requesting the storage key;

registering a translation result of the logical address in the translation lookaside buffer;

initiating a retrieval search of the translation lookaside buffer again, without waiting for receipt of the requested storage key thereby enabling a search of the translation lookaside buffer device for a successive data access without waiting for the requested storage key to be received; and

transmitting data stored in a cache corresponding to the logical address.

8. An apparatus as recited in claim 7, wherein the transferring transfers the data retrieved from the cache to an instruction processor without waiting for arrival of the requested storage key.

9. An cache control device used for a data processing device provided with key control protection using a storage key for an access to data, comprising:

cache means for storing the data;

translation lookaside means for storing a correspondence between a logical address and a physical address

request means for requesting the storage key;

control means for initiating a retrieval of the data in the cache means without waiting for receipt of the requested storage key thereby enabling a search of the translation lookaside means for a successive data access without waiting for the requested storage key to be received, thereby enabling a search of the translation lookaside buffer device for a successive data access without waiting for the requested storage key to be received; and

transfer means for transmitting the retrieved data.

10. An apparatus as recited in claim 9, wherein the transfer means transfers the data retrieved from the cache to an instruction processor without waiting for arrival of the requested storage key.