Reconfigurable data path processor
First Claim
1. A method of processing data through reconfigurable data path processor comprising a plurality of independent processing elements, including first processing element comprising a first PE output, and a conditional multiplexer with a first multiplexer input, a second multiplexer input and a first multiplexer output, the method comprising the steps:
- a. processing a first data set according to a first algorithm within the first processing element, wherein the first data set comprises a first processable value and a second processable value;
b. generating a first processed output according to the processing of the first data set;
c. generating a first set of arithmetic status bits according to the processing of the first data set through the first algorithm;
d. sending the first set of arithmetic status bits to a first arithmetic status bit output;
d. evaluating the first set of arithmetic status bits; and
e. establishing a first data path through the conditional multiplexer according to the evaluation of the first set of arithmetic status bits, wherein the first data path is selected from among a data path connecting the first multiplexer input to the first multiplexer output and a data path coupling the second multiplexer input to the first multiplexer output.
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Abstract
A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.
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Citations
42 Claims
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1. A method of processing data through reconfigurable data path processor comprising a plurality of independent processing elements, including first processing element comprising a first PE output, and a conditional multiplexer with a first multiplexer input, a second multiplexer input and a first multiplexer output, the method comprising the steps:
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a. processing a first data set according to a first algorithm within the first processing element, wherein the first data set comprises a first processable value and a second processable value;
b. generating a first processed output according to the processing of the first data set;
c. generating a first set of arithmetic status bits according to the processing of the first data set through the first algorithm;
d. sending the first set of arithmetic status bits to a first arithmetic status bit output;
d. evaluating the first set of arithmetic status bits; and
e. establishing a first data path through the conditional multiplexer according to the evaluation of the first set of arithmetic status bits, wherein the first data path is selected from among a data path connecting the first multiplexer input to the first multiplexer output and a data path coupling the second multiplexer input to the first multiplexer output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. An ultra low power reconfigurable data path processor for processing data, comprising a plurality of processing elements, a first processing element comprising:
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a. a conditional multiplexer comprising;
i. a first multiplexer input;
ii. a second multiplexer input;
iii. a first multiplexer output; and
vi. a first multiplexer control configured to select a data path according to a binary state of an arithmetic status input, the data path selected from among a first data path coupling the first multiplexer input with the first multiplexer output and a second data path coupling the second multiplexer input with the first multiplexer output; and
b. a first processing component comprising;
i. a first partially processed data input;
ii. a first processed-data output; and
iii. a first arithmetic status output, wherein the first arithmetic status output is configured to transmit a binary status of at least one select arithmetic status bit generated during data processing of the first processing component, the first arithmetic status output being couplable with the arithmetic status input of the first multiplexer. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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Specification