Reconfigurable data path processor

• US 6,883,084 B1
• Filed: 07/25/2002
• Issued: 04/19/2005
• Est. Priority Date: 07/25/2001
• Status: Active Grant

• Current Assignee: Science & Technology Corporation
• Original Assignee: The University of New Mexico
• Inventors: Donohoe, Gregory
• Primary Examiner(s): Treat, William M.
• Application Number:
  US10/206,517
• Time in Patent Office: 999 Days
• Field of Search: 71/1, 71/10, 71/11, 71/15, 71/16
• US Class Current: 712/1
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.

Claims

1. A method of processing data through reconfigurable data path processor comprising a plurality of independent processing elements, including first processing element comprising a first PE output, and a conditional multiplexer with a first multiplexer input, a second multiplexer input and a first multiplexer output, the method comprising the steps:

a. processing a first data set according to a first algorithm within the first processing element, wherein the first data set comprises a first processable value and a second processable value;

b. generating a first processed output according to the processing of the first data set;

c. generating a first set of arithmetic status bits according to the processing of the first data set through the first algorithm;

d. sending the first set of arithmetic status bits to a first arithmetic status bit output;

d. evaluating the first set of arithmetic status bits; and

e. establishing a first data path through the conditional multiplexer according to the evaluation of the first set of arithmetic status bits, wherein the first data path is selected from among a data path connecting the first multiplexer input to the first multiplexer output and a data path coupling the second multiplexer input to the first multiplexer output.

2. The method according to claim 1 wherein the step of processing a first data set is preceded by the step of configuring the first processing element.

3. The method according to claim 2 wherein the step of configuring the first processing element comprises the step of configuring a first plurality of data paths within the first processing element.

4. The method according to claim 2 further comprising a logical mask with a mask register and mask logic, wherein the step of configuring the first processing element comprises the step of downloading a binary mask pattern into the mask register.

5. The method according to claim 4 wherein the step of evaluating the first set of arithmetic status bits comprises the step of comparing the first set of arithmetic status bits to the binary mask pattern according to the mask logic.

6. The method according to claim 2 wherein the step of configuring the first processing element comprises the step of transmitting a first PE configuration message.

7. The method according to claim 2 further comprising the step of configuring a second plurality of data paths interconnecting the plurality of processing elements within the reconfigurable data path processor.

8. The method according to claim 7 wherein the step of configuring the second plurality of data paths comprises the step of transmitting a first pipeline configuration message.

9. The method according to claim 7 wherein the second plurality of data paths are configured within a hierarchical network of configurable data paths.

10. The method according to claim 2 further comprising the steps of:

a. processing a second data set according to a second algorithm within the first processing element, wherein the second data set comprises a third processable value and a fourth processable value;

b. generating a second processed output according to the processing of the second data set;

c. generating a second set of arithmetic status bits according to the processing of the second data set through the second algorithm; and

d. sending the second set of arithmetic status bits to a second arithmetic status output.

11. The method according to claim 10 wherein the first processing element comprises a first selective multiplexer with a third multiplexer input coupled to the first arithmetic status output, a fourth multiplexer input coupled to the second arithmetic status output, and a second multiplexer output, wherein the step of configuring a first plurality of data paths further comprises the step of configuring a path from the third multiplexer input to the second multiplexer output.

12. The method according to claim 10 wherein the first algorithm includes an arithmetic logic unit with a first ALU input, a second ALU input, and an ALU output, and the second algorithm includes a multiplier with a first MUL input, a second MUL input and a MUL output, the method further comprising the steps:

a. inputting the first processable value into the first ALU input;

b. inputting the second processable value into the second ALU input;

c. inputting the third processable value into the first MUL input; and

d. inputting the fourth processable value-into the second MUL input.

13. The method according to claim 10 wherein the first algorithm includes a multiplier and the second algorithm includes an arithmetic logic unit.

14. The method according to claim 3 wherein the processing element comprises a crossbar-switch with a plurality of crossbar-switch inputs and a plurality of crossbar-switch outputs including a first crossbar switch output and a second crossbar switch output, and wherein the step of configuring a plurality of data paths within the processing element comprises the step of controllably coupling a first input from among the plurality of crossbar-switch inputs to a first output from among the plurality of crossbar-switch outputs.

15. The method according to claim 2 wherein the step of configuring the first processing element comprises the step of downloading a first pre-determined value into a first constant-data register.

16. The method according to claim 12 wherein the first algorithm further comprises an first output shifter, a first rounding module and a first clipping module, and the second algorithm further comprises a second shifter, a second rounding module and a second clipping module.

17. The method according to claim 12 wherein the first processable value is derived from an output of the multiplier.

18. The method according to claim 12 wherein the third processable value is derived from an output of the arithmetic logic unit.

19. The method according to claim 13 further comprising a first constant data register configured to store a first fixed binary value, a second constant data register configured to store a second fixed binary value, a first PE input configured to receive a first binary input value, a second PE input configured to receive a second binary input value, and a third PE input configured to receive a third binary input value, the method further comprising the steps of:

a. selecting the first processable value from among the first fixed binary value and the first binary input value;

b. selecting the second processable value from among an output value derived from the arithmetic logic unit and the second binary input value;

c. selecting the third processable value from among an output value derived from the multiplier and the second binary input value; and

d. selecting the fourth processable value from among the second fixed binary value and the third binary input value.

20. The method according to claim 2 further comprising the steps:

a. downloading a binary output value from the first multiplexer output to an output register;

b. triggering the output register with a fire_PE control signal; and

c. transmitting the binary output value from the output register to the first PE output.

21. The method according to claim 20 further comprising a second processing element with a fourth PE input and a second PE output, and a third processing element with a fifth PE input and a third PE output, wherein an output of the first PE is coupled to the fourth PE input, and an output of the first PE is coupled to the 5^th PE input, whereby the first processing element forms a source of divergence for a parallel processing configuration.

22. The method according to claim 21 wherein the reconfigurable data path processor is a ULP CMOS circuit.

23. The method according to claim 22 further comprising the steps:

a. integrating the reconfigurable data path processor into a spacecraft; and

b. shooting the spacecraft into outer space.

24. The method according to claim 20 further comprising

second processing element with a second PE output coupled to an input of the first processing element selected from among the first PE input, the second PE input and the third PE input, and a third processing element with a third PE output coupled to an input of the first processing element selected from among the first PE input, the second PE input and the third PE input, whereby the first processing element forms a convergence of a parallel processing configuration.

25. An ultra low power reconfigurable data path processor for processing data, comprising a plurality of processing elements, a first processing element comprising:

a. a conditional multiplexer comprising;

i. a first multiplexer input;

ii. a second multiplexer input;

iii. a first multiplexer output; and

vi. a first multiplexer control configured to select a data path according to a binary state of an arithmetic status input, the data path selected from among a first data path coupling the first multiplexer input with the first multiplexer output and a second data path coupling the second multiplexer input with the first multiplexer output; and

b. a first processing component comprising;

i. a first partially processed data input;

ii. a first processed-data output; and

iii. a first arithmetic status output, wherein the first arithmetic status output is configured to transmit a binary status of at least one select arithmetic status bit generated during data processing of the first processing component, the first arithmetic status output being couplable with the arithmetic status input of the first multiplexer.

26. The ultra low power reconfigurable data path processor according to claim 25 wherein the first multiplexer control comprises a data mask disposed between the arithmetic status input and a first multiplexer control input, the data mask comprising a mask input, a mask register for storing a pre-determined binary mask, mask logic, and a mask output, wherein the arithmetic status input is coupled to the mask and the mask output is coupled to the first multiplexer control input, such that the mask logic is configured to control a value of the mask output according to a comparison of a binary state of the at least one select arithmetic status bit with select bits within the pre-determined binary mask.

27. The reconfigurable data path processor of claim 26 wherein the data mask is integral to the conditional multiplexer.

28. The ultra low power reconfigurable data path processor according to claim 26 wherein the at least one select arithmetic status bit comprises a plurality of bits, including a zero status bit, a negative status bit, an overflow status bit and an underflow status bit.

29. The ultra low power reconfigurable data path processor according to claim 26 further comprising a first major processing component with a first and second major input and a first major output, wherein the major first major output is coupled to the first partially processed data input of the first processing component.

30. The ultra low power reconfigurable data path processor according to claim 29 further comprising:

a. a second major processing component having a third and fourth major input and a second major output;

b. a second processing component comprising

i. a second partially processed data input;

ii. a second processed data output; and

iii. a second arithmetic status output; and

c. a first selective multiplexer comprising;

i. a third multiplexer input;

ii. a fourth multiplexer input; and

iii. a second multiplexer output, wherein the first selective multiplexer is configurable to selectively establish a data path selected from among a third data path coupling third multiplexer input to the second multiplexer output and a fourth data path coupling the fourth multiplexer input to the second multiplexer output, and wherein the second major output is coupled to the second partially processed data input, and wherein the first arithmetic status output is coupled to the third multiplexer input and the second arithmetic status output is coupled with the fourth multiplexer input.

31. The ultra low power reconfigurable data path processor according to claim 30 wherein the first major processing component is selected from among a group consisting of arithmetic logic units and multipliers, and the second major processing component is selected from among a group consisting of arithmetic logic units and multipliers.

32. The ultra low power reconfigurable data path processor according to claim 31 further comprising a crossbar switch comprising a plurality of crossbar inputs including a first crossbar input and a second crossbar input, and a plurality of crossbar outputs including a first crossbar output and a second crossbar output, wherein the crossbar switch is configurable to selectively route any crossbar input to any crossbar output.

33. The ultra low power reconfigurable data path processor according to claim 32 further comprising:

a. a second selective multiplexer comprising

i. a fifth multiplexer input;

ii. a sixth multiplexer input; and

iii. a third multiplexer output, wherein the second selective multiplexer is configurable to selectively establish a data path selected from among a fifth data path coupling the fifth multiplexer input to the third multiplexer output and a sixth data path coupling the sixth multiplexer input to the third multiplexer output, and

b. a third selective multiplexer comprising

i. a seventh multiplexer input;

ii. an eighth multiplexer input; and

iii. a fourth multiplexer output, wherein the third selective multiplexer is configurable to selectively establish a data path selected from among a seventh data path coupling the seventh multiplexer input to the fourth multiplexer output and an eighth data path coupling the eighth multiplexer input to the fourth multiplexer output, and wherein and wherein a first crossbar output is coupled to the fifth multiplexer input, the second processed data output is coupled to the sixth multiplexer input, the second crossbar output is coupled to the seventh multiplexer input, the first processed data output is coupled to the eighth multiplexer input, the third multiplexer output is coupled to the first multiplexer input, and the fourth multiplexer output is coupled to the second multiplexer input.

34. The reconfigurable data path processor of claim 33 wherein the first crossbar input is selected from a group consisting of a first processing element input, a second processing element input, a third processing element input, a first constant data register and a second constant data register, and wherein the second crossbar input is selected from a group consisting of a first processing element input, a second processing element input, a third processing element input, a first constant data register and a second constant data register.

35. The reconfigurable data path processor of claim 34 wherein the first major input is coupled to a terminal selected from among the second processed data output and the first processing element input, and wherein the second major input is coupled to a terminal selected from among the first constant data register and the second processing element input, and wherein the third major input is couple to a terminal selected from among the second constant data register and the third processing element input, and the fourth major input is coupled to a terminal selected from among the first processing element input and the first processed data output.

36. The reconfigurable data path processor according to claim 35 further comprising a third crossbar output, wherein the first multiplexer output is controllably coupled to a first processing element output and the third crossbar output is controllably coupled to a second processing element output.

37. The reconfigurable data path processor according to claim 36 further comprising

a. a second processing element with a fourth processing element input coupled to an output of the first processing element, thereby forming a ninth data path;

and

b. a third processing element with a fifth processing element input coupled to an output of the first processing element, thereby forming a tenth data path, thereby forming a parallel path divergence.

38. The reconfigurable data path processor according to claim 36 further comprising

a. a second processing element with a third processing element output coupled to an input of the first processing element, thereby forming a ninth data path;

and

b. a third processing element with a fourth processing element output coupled to an input of the first processing element, thereby forming a tenth data path, thereby forming a parallel path convergence.

39. The reconfigurable data path processor according to claim 37 wherein the ninth and tenth data paths are formed through a pipeline configuration command.

40. The reconfigurable data path processor according to claim 37 wherein the second processing element and the third processing element are configured to process data simultaneously.

41. The reconfigurable data path processor according to claim 33 wherein the second selective multiplexer is configurable to selectively establish a data path selected from among a fifth data path coupling the fifth multiplexer input to the third multiplexer output and a sixth data path coupling the sixth multiplexer input to the third multiplexer output according to a processing element configuration message.

42. The reconfigurable data path processor according to claim 37 wherein the first major processing component and the second major processing component comprise a radiation tolerant ultra low power CMOS circuit configured for use in outer space.