Apparatus and method for performing power management functions

• US 6,883,102 B2
• Filed: 12/18/2001
• Issued: 04/19/2005
• Est. Priority Date: 12/18/2001
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Rasmussen, Kim, Williams, Gerard Richard III, Flynn, David Walter
• Primary Examiner(s): Browne, Lynne H.
• Assistant Examiner(s): HENRY, MATTHEW ALLAN
• Application Number:
  US10/020,511
• Publication Number:
  US 20030115491A1
• Time in Patent Office: 1,218 Days
• Field of Search: 713/300, 717/134, 717/124
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power

Abstract

The present invention provides a data processing apparatus and method for testing power management instructions. The data processing apparatus comprises a processor for executing data processing instructions including power management instructions, at least one of the power management instructions being a command power management instruction. A power management controller is also provided for receiving command data from the processor when a command power management instruction is executed by the processor, and to control power management logic to perform an associated set of power management functions dependent on the command data. The data processing apparatus includes first power management logic controllable by the power management controller, with the power management controller also having an interface to enable communication with additional power management logic. In accordance with the present invention, the processor is arranged when executing the command power management instruction to specify within the command data provided to the power management controller whether an emulation mode of operation is set. The power management controller is arranged when the emulation mode is not set to initiate the associated set of power management functions dependent on the command data, whilst if the emulation mode is set it is arranged to only initiate a subset of the associated set of power management functions not requiring communication over the interface. By this approach, it is possible to perform some testing of power management software before all aspects of the power management hardware have been designed.

Claims

1. A data processing apparatus, comprising:

a processor for executing data processing instructions including power management instructions, at least one of said power management instructions being a command power management instruction;

a power management controller for receiving command data from the processor when a command power management instruction is executed by the processor, and to control power management logic to perform an associated set of power management functions dependent on said command data;

first power management logic controllable by the power management controller;

the power management controller having an interface to enable communication with additional power management logic;

the processor being arranged when executing said command power management instruction to specify within said command data provided to the power management controller whether an emulation mode of operation is set, said power management controller being arranged when said emulation mode is not set to initiate said associated set of power management functions dependent on said command data, and being arranged when said emulation mode is set to only initiate a subset of said associated set of power management functions not requiring communication over said interface.

2. A data processing apparatus as claimed in claim 1, wherein said first power management logic comprises one or more power management isolation layers, each power management isolation layer being associated with a component of the data processing apparatus, and being controllable by the power management controller to isolate the associated component from other components of the data processing apparatus dependent on the command power management instruction being executed by the processor.

3. A data processing apparatus as claimed in claim 2, further comprising one or more additional processors, each processor having one of said power management isolation layers associated therewith.

4. A data processing apparatus as claimed in claim 1, wherein a handshake protocol is employed between the processor and the power management controller, such that when said processor issues said command data to said power management controller, said power management controller issues an acknowledgement signal to the processor to acknowledge receipt of the command data.

5. A data processing apparatus as claimed in claim 1, further comprising a communication path coupling said processor and said power management controller, said communication path including a transmit channel on which the processor is arranged to issue said command data to the power management controller.

6. A data processing apparatus as claimed in claim 5, wherein said processor includes a transmit register for storing said command data to be issued over said transmit channel.

7. A data processing apparatus as claimed in claim 6, wherein said emulation mode is specified by the value of a field within the transmit register.

8. A data processing apparatus as claimed in claim 1, wherein in said emulation mode, once said subset of said associated set of power management functions have been performed, said power management controller is arranged to emulate a reset function to cancel said subset of said associated set of power management functions.

9. A data processing apparatus as claimed in claim 8, wherein following said reset function, the processor is arranged to execute a status power management instruction to cause a request to be issued to the power management controller for status data identifying the status of the data processing apparatus after execution of said command power management instruction.

10. A data processing apparatus as claimed in claim 9, wherein said power management controller includes a status register and is arranged to store said status data in the status register after performance of said associated set of power management functions, the processor including a receive register for storing the status data as provided by the power management controller upon receipt of said request.

11. A data processing apparatus as claimed in claim 10, further comprising a communication path coupling said processor and said power management controller, said communication path comprising a transmit channel on which the processor is arranged to issue said command data to the power management controller, and a receive channel on which the processor is arranged to issue said request to said power management controller and on which the power management controller is arranged to return said status data.

12. A data processing apparatus as claimed in claim 11, wherein said processor further includes a channel status register for storing a first flag indicating whether the transmit channel is busy and a second flag for indicating whether the receive channel is busy.

13. A data processing apparatus as claimed in claim 1, wherein said processor comprises a processor core and a coprocessor and said coprocessor is arranged to execute said power management instructions.

14. A method of operating a data processing apparatus to test power management instructions, comprising the steps of:

(a) executing on a processor a command power management instruction to generate command data;

(b) issuing said command data to a power management controller;

(c) controlling, via the power management controller, power management logic to perform an associated set of power management functions dependent on said command data, the data processing apparatus having first power management logic controllable by the power management controller, and the power management controller having an interface to enable communication with additional power management logic;

at said step (a), the processor being arranged when executing said command power management instruction to specify within said command data provided to the power management controller whether an emulation mode of operation is set; and

at said step (c), said power management controller being arranged when said emulation mode is not set to initiate said associated set of power management functions dependent on said command data, and being arranged when said emulation mode is set to only initiate a subset of said associated set of power management functions not requiring communication over said interface.

15. A method as claimed in claim 14, wherein said first power management logic comprises one or more power management isolation layers, each power management isolation layer being associated with a component of the data processing apparatus, and being controllable by the power management controller at said step (c) to isolate the associated component from other components of the data processing apparatus dependent on the command power management instruction being executed by the processor.

16. A method as claimed in claim 15, wherein the data processing apparatus further comprises one or more additional processors, each processor having one of said power management isolation layers associated therewith.

17. A method as claimed in claim 14, further comprising the step of employing a handshake protocol between the processor and the power management controller, such that when said processor issues said command data to said power management controller at said step (b), said power management controller issues an acknowledgement signal to the processor to acknowledge receipt of the command data.

18. A method as claimed in claim 14, further comprising the step of providing a communication path coupling said processor and said power management controller, said communication path including a transmit channel on which the processor is arranged to issue said command data to the power management controller at said step (b).

19. A method as claimed in claim 18, wherein said processor includes a transmit register for storing said command data to be issued over said transmit channel.

20. A method as claimed in claim 19, wherein said emulation mode is specified by the value of a field within the transmit register.

21. A method as claimed in claim 14, wherein in said emulation mode, once said subset of said associated set of power management functions have been performed, the method further comprises the step of causing said power management controller to emulate a reset function to cancel said subset of said associated set of power management functions.

22. A method as claimed in claim 21, wherein following said reset function, the method further comprises the step of executing on said processor a status power management instruction to cause a request to be issued to the power management controller for status data identifying the status of the data processing apparatus after execution of said command power management instruction.

23. A method as claimed in claim 22, wherein said power management controller includes a status register and is arranged to store said status data in the status register after performance of said associated set of power management functions, the processor including a receive register for storing the status data as provided by the power management controller upon receipt of said request.

24. A method as claimed in claim 23, further comprising the step of providing a communication path coupling said processor and said power management controller, said communication path comprising a transmit channel on which the processor is arranged to issue said command data to the power management controller, and a receive channel on which the processor is arranged to issue said request to said power management controller and on which the power management controller is arranged to return said status data.

25. A method as claimed in claim 24, further comprising the step of providing said processor with a channel status register for storing a first flag indicating whether the transmit channel is busy and a second flag for indicating whether the receive channel is busy.

26. A method as claimed in claim 14, wherein said processor comprises a processor core and a coprocessor and said coprocessor is arranged to execute said power management instructions.

27. A computer program product carrying a computer program for controlling an apparatus in accordance with the method of claim 14.