System and method for temporally isolating environmentally sensitive integrated circuit faults

• US 6,883,113 B2
• Filed: 04/18/2002
• Issued: 04/19/2005
• Est. Priority Date: 04/18/2002
• Status: Expired due to Fees

• Current Assignee: Frantorf Investments GmbH LLC (Intellectual Ventures LLC)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Todd, Ronald, Storey, Thomas M., McWilliam, Bruce
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): PUENTE, EMERSON C
• Application Number:
  US10/125,900
• Publication Number:
  US 20030200484A1
• Time in Patent Office: 1,097 Days
• Field of Search: 714/17, 714/29, 714/30, 714/35, 714/37, 324763-765
• US Class Current: 714/17
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/318552 Clock circuits details

Abstract

A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle T_max at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log₂ (T_max+1) iterations.

Claims

1. A method for temporally isolating a fault within an integrated circuit comprising the steps of:

determining a marginally failing environmental condition associated with the fault;

determining a clock cycle at which the fault was first detected; and

applying a plurality of first test pattern subsets under the marginally failing environmental condition,

wherein each first test pattern subset is applied from an initial clock cycle through a unique candidate clock cycle.

2. The method of claim 1, wherein a first candidate clock cycle is temporally earlier than the clock cycle at which the fault was first detected.

3. The method of claim 1, wherein each candidate clock cycle is temporally earlier than the clock cycle at which the fault was first detected.

4. The method of claim 1, wherein each first test pattern subset comprises a unique number of test patterns.

5. The method of claim 1, wherein a candidate clock cycle has a value based upon whether the fault appeared during application of a most recent first test pattern subset under the marginally failing environmental condition.

6. The method of claim 1, further comprising the step of adjusting a candidate clock cycle to an earlier clock cycle in the event that the fault appeared during application of a most recent first test pattern subset under the marginally failing environmental condition.

7. The method of claim 1, further comprising the step of adjusting a candidate clock cycle to a later clock cycle in the event that the fault was absent during application of a most recent first test pattern subset under the marginally failing environmental condition.

8. The method of claim 1, further comprising the step of adjusting a candidate clock cycle in accordance with a binary search technique based upon whether the fault occurred during application of a most recent first test pattern subset under the marginally failing environmental condition.

9. The method of claim 1, further comprising the step of determining a minimally passing environmental condition associated with the fault.

10. The method of claim 9, wherein determination of the marginally failing environmental condition and determination of the minimally passing environmental condition is determined through a schmoo operation.

11. The method of claim 1, further comprising the steps of:

determining a minimally passing environmental condition associated with the fault; and

applying a plurality of second test pattern subsets under the minimally passing environmental condition.

12. The method of claim 1, wherein the determination of the marginally failing environmental condition is performed through a schmoo operation.

13. A method for temporally isolating a fault within an integrated circuit comprising the steps of:

determining a marginally failing environmental condition associated with the fault;

identifying a clock cycle T_max at which the fault was first detected;

determining a candidate clock cycle at which the fault may have occurred;

iteratively performing the substeps of;

applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; and

adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application; and

determining an exact clock cycle at which the fault occurred in a maximum of Log₂ (T_max+1) substep iterations.

14. A method for temporally isolating a fault within an integrated circuit comprising the steps of:

determining a marginally failing environmental condition associated with the fault;

determining an upper bound clock cycle corresponding to a latest clock cycle at which the fault may have occurred;

determining a lower bound clock cycle corresponding to an earliest clock cycle at which the fault may have occurred;

determining a candidate clock cycle at which the fault may have occurred;

applying a test pattern subset from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; and

adjusting the candidate clock cycle and one from the group of the upper bound clock cycle and the lower bound clock cycle based upon whether the fault occurred during test pattern subset application.

15. The method of claim 14, wherein the adjusting step comprises the substeps of:

setting the upper bound clock cycle to the candidate clock cycle; and

setting the candidate clock cycle to an earlier occurring clock cycle.

16. The method of claim 14, wherein the adjusting step comprises the substeps of:

setting the upper bound clock cycle to the candidate clock cycle; and

setting the candidate clock cycle to an earlier occurring clock cycle in accordance with a binary search technique.

17. The method of claim 14, wherein the adjusting step comprises the substeps of:

setting the lower bound clock cycle to the candidate clock cycle; and

setting the candidate clock cycle to a later occurring clock cycle.

18. The method of claim 14, wherein the adjusting step comprises the substeps of:

setting the lower bound clock cycle to the candidate clock cycle; and

setting the candidate clock cycle to a later occurring clock cycle in accordance with a binary search technique.

19. The method of claim 14, further comprising the step of performing the applying and adjusting steps a plurality of times.

20. The method of claim 14, further comprising the step of performing the applying and adjusting steps until a most recent candidate clock cycle identifies an exact clock cycle at which the fault was first activated.