Secure credit card employing pseudo-random bit sequences for authentication

• US 6,883,717 B1
• Filed: 04/14/2004
• Issued: 04/26/2005
• Est. Priority Date: 04/14/2004
• Status: Expired due to Term

• Current Assignee: Kyndryl Incorporated (Kyndryl Holdings, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kelley, Edward E., Motika, Franco
• Primary Examiner(s): Stcyr, Daniel
• Assistant Examiner(s): Hess, Daniel A.
• Application Number:
  US10/709,112
• Time in Patent Office: 377 Days
• Field of Search: 235/380, 235/492
• US Class Current: 235/492
• CPC Class Codes: G06F 2207/581 Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/40145 Biometric identity checks
• CPC Class Codes: G06Q 20/40975 using encryption therefor
• CPC Class Codes: G07F 19/00 Complete banking systems; Coded card-freed arrangements adapted for dispensing or receiving monies or the like and posting such transactions to existing accounts, e.g. automatic teller machines data processing equipment for bank accounting G06Q40/02
• CPC Class Codes: G07F 7/08 by coded identity card or credit card or other personal identification means without personal verification means G07F7/02
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G07F 7/1016 Devices or methods for securing the PIN and other transaction-data, e.g. by encryption arrangements for secret communication, see H04L9/00
• CPC Class Codes: G07F 7/12 Card verification

Abstract

A secure credit card has a pair of linear feedback shift registers (LFSRs) for generating a pair of random numbers. The LFSRs each have a unique initial state and feedback tap configuration. Hence, they each produce a unique sequence of numbers. When a financial transaction occurs, the LFSRs are operated for a random number of clock cycles, to create a pair of matched random numbers. Each card issued has unique LFSR settings, and so will produce characteristic random numbers. At a financial institution, the LFSR settings are known, so the financial institution can determine by calculation if the pair of random numbers is authentic. There are many variations, including a credit card with a secret security code for activation, and 2-way “handshake” communication with the financial institution. Also, one of the LFSRs may be replaced with a binary, or similar counter.

Claims

1. A secure credit card, comprising:

a) a counter;

b) a pseudo-random bit sequence generator;

c) a clock for driving the counter and for driving the pseudo-random bit sequence generator, wherein the clock is operable for an unpredictable number of cycles, wherein the unpredictable number of cycles is determined by a human action of unpredictable duration.

2. The secure credit card of claim 1 wherein the counter is a first linear feedback shift register (LFSR).

3. The secure credit card of claim 2 wherein the first LFSR has a different initial state compared to other issued credit cards.

4. The secure credit card of claim 2 wherein the first LFSR has a different configuration compared to other issued credit cards.

5. The secure credit card of claim 2 wherein the first LFSR is configured to have a sequence length of 2ⁿ−

1, where n is a number of stages in the shift register.

6. The secure credit card of claim 2 wherein the first LFSR has an initial state and configuration set by electronic fuses.

7. The secure credit card of claim 1 wherein the pseudo-random bit sequence generator is a second linear feedback shift register (LFSR).

8. The secure credit card of claim 7 wherein the second LFSR has a different initial state compared to other issued credit cards.

9. The secure credit card of claim 7 wherein the second LFSR has a different configuration compared to other issued credit cards.

10. The secure credit card of claim 7 wherein the second LFSR is configured to have a sequence length of 2ⁿ−

1, where n is a number of stages in the shift register.

11. The secure credit card of claim 7 wherein the second LFSR has an initial state and configuration set by electronic fuses.

12. The secure credit card of claim 1 wherein the clock drives the first counter and the second pseudo random bit generator for the same number of cycles.

13. The secure credit card of claim 1 wherein the clock drives the first counter and the second pseudo random bit generator for numbers of cycles having a fixed mathematical relationship.

14. The secure credit card of claim 1 wherein the clock has a clock speed in the range of about 0.1-100 megahertz.

15. The secure credit card of claim 1 wherein the first counter and second pseudo-random bit sequence generators are virtual entities emulated in an electronic processor.

16. The secure credit card of claim 1 further comprising a display for displaying numbers produced by the first counter and the second pseudo random bit generator.

17. The secure credit card of claim 1, further comprising a means for activating the card for a desired time duration.

18. The secure credit card of claim 1, further comprising a means for activating the card for a desired number of transactions.

19. The secure credit card of claim 1, further comprising a means for resetting a secure access code or PIN.

20. The secure credit card of claim 1 wherein said unpredictable number of cycles is determined by a human action of unpredictable duration is determined by one of a duration a keypad is pressed, a duration between two keypad entries, or a duration between card activation and communication with a card reader.

21. A secure credit card, comprising:

a) a virtually emulated first linear-feedback shift register (LFSR);

b) a second linear-feedback shift register (LFSR) or a second virtually emulated LFSR; and

c) a clock for driving the first and second linear-feedback shift registers, wherein the clock is operable for an unpredictable number of cycles, wherein the unpredictable number of cycles is determined by a human action of unpredictable duration.

22. The secure credit card of claim 21 wherein the first LFSR and second LFSR have different initial states compared to other issued credit cards.

23. The secure credit card of claim 21 wherein the first LFSR and second LFSR have different configurations compared to other issued credit cards.

24. The secure credit card of claim 21 wherein the first LFSR and second LFSR are configured to have a sequence length of 2 where n is a number of shift register stages.

25. The secure credit card of claim 21 wherein the first LFSR and second LFSR each have an initial state and configuration set by electronic fuses.

26. The secure credit card of claim 21 wherein the clock drives the first LFSR and the second LFSR for the same number of cycles.

27. The secure credit card of claim 21 wherein the clock drives the first LFSR and the second LFSR for numbers of cycles having a fixed mathematical relationship.

28. A method for authenticating a secure credit card having a linear feedback shift register (LFSR), comprising the steps of:

a) sending from the credit card to a financial institution a card identification number uniquely associated with LFSR settings;

c) sending from the financial institution to the credit card a request for an output of the LFSR after m clock cycles;

d) operating the LFSR for m clock cycles to produce an LFSR output;

e) sending the LFSR output from the card to the financial institution;

f) comparing the LFSR output with LFSR settings for the credit card to authenticate the credit card.

29. The method of claim 28 further comprising the step of looking up in a database at the financial institution the settings information associated with the card identification number.

30. A method for authenticating a secure credit card having a counter and a pseudo-random bit sequence generator (GEN), comprising the steps of:

a) driving the counter and the GEN for numbers of cycles having a fixed or predictable mathematical relationship;

b) transmitting to a financial institution outputs of the counter and GEN after step (a);

c) authenticating the credit card by comparing the outputs produced in step (b) with settings of the counter and GEN known to the financial institution.

31. The method of claim 30 wherein the counter and GEN are driven for the same number of cycles.

32. The method of claim 30 wherein the unpredictable number of cycles is determined by a clock operated for an unpredictable duration.

33. The method of claim 32 wherein the unpredictable duration is determined by a human action.

34. The method of claim 33 wherein said human action is determined by one of a duration a keypad is pressed, a duration between two keypad entries, or a duration between card activation and communication with a card reader.

35. The method of claim 30 wherein in said driving step, said counter and GEN are each driven for a plurality of cycles.