Die stacking scheme

• US 6,884,658 B2
• Filed: 11/16/2001
• Issued: 04/26/2005
• Est. Priority Date: 03/30/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US09/992,580
• Publication Number:
  US 20020137258A1
• Time in Patent Office: 1,257 Days
• Field of Search: 438/109
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85207 Thermosonic bonding
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

An improved die stacking scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate, first and second semiconductor dies, and at least one decoupling capacitor. The first semiconductor die defines a first active surface. The first active surface includes at least one conductive bond pad. The second semiconductor die defines a second active surface, the second active surface includes at least one conductive bond pad. The first semiconductor die is interposed between the substrate and the second semiconductor die such that a surface of the second semiconductor die defines an uppermost die surface of the multiple die semiconductor assembly and such that a surface of the first semiconductor die defines a lowermost die surface of the multiple die semiconductor assembly. The decoupling capacitor is secured to the uppermost die surface and is conductively coupled to at least one of the first and second semiconductor dies.

Claims

1. A method of assembling a printed circuit board, said method comprising:

providing a substrate including a first surface and conductive contacts included on said first surface;

providing a first semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said first die defines a first active surface,

the other of said major surfaces of said first die defines a first stacking surface, and

said first active surface includes a plurality of conductive bond pads;

electrically coupling said first active surface to said substrate with a plurality of topographic contacts extending from respective conductive bond pads on said first active surface to corresponding conductive contacts on said first surface of said substrate;

providing a second semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said second die defines a second active surface,

the other of said major surfaces of said second die defines a second stacking surface,

said second active surface includes a plurality of conductive bond pads, and

said first stacking surface is devoid of conductive bond pads;

securing said first stacking surface to said second stacking surface;

securing a single decoupling capacitor to said second active surface;

providing a pair of conductive lines, each of said conductive lines connecting a terminal of said decoupling capacitor, a bond pad on said second active surface, and a conductive contact on said first surface of said substrate;

electrically coupling said conductive contact on said first surface of said substrate to said first semiconductor die via one of said plurality of topographic contacts extending from respective conductive bond pads on said first active surface to corresponding conductive contacts on said first surface of said substrate;

arranging said pair of conductive lines such that said decoupling capacitor is connected across V_ss and V_cc pins of said first and second semiconductor dies;

positioning a printed circuit board such that a first surface of said printed circuit board faces said substrate; and

providing a plurality of topographic contacts extending from said substrate to said first surface of said printed circuit board.

2. A method of stacking a plurality of semiconductor die, said method comprising:

providing a substrate including a first surface and conductive contacts included on said first surface;

providing a first semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said first die defines a first active surface,

the other of said major surfaces of said first die defines a first stacking surface, and

said first active surface includes at least one conductive bond pad;

electrically coupling said first active surface to said substrate by at least one topographic contact extending from a conductive bond pad on said first active surface to a conductive contact on said first surface of said substrate;

providing a second semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said second die defines a second active surface,

the other of said major surfaces of said second die defines a second stacking surface, and

said second active surface includes at least one conductive bond pad;

securing said first stacking surface to said second stacking surface;

securing at least one decoupling capacitor to said second active surface; and

providing at least one conductive line connecting said decoupling capacitor, a bond pad on said second active surface, and a conductive contact on said first surface of said substrate.

3. The method as claimed in claim 2 further comprising providing at least one conductive line extending from a bond pad on said second active surface to a conductive contact on said first surface of said substrate.