Enhanced adhesion strength between mold resin and polyimide

• US 6,884,662 B1
• Filed: 01/28/2002
• Issued: 04/26/2005
• Est. Priority Date: 01/28/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsao, Pei-Haw, Chen, Ken, Huang, Chender, Wang, Jones, Huang, Hank
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Toledo, Fernando L.
• Application Number:
  US10/058,473
• Time in Patent Office: 1,184 Days
• Field of Search: 438/124, 438/127, 438/129
• US Class Current: 438/124
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/351 Thermal stress

Abstract

A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.

Claims

1. A method of creating an interface layer over the surface of a semiconductor device, comprising the steps of:

providing a semiconductor device, said semiconductor device having a first and a second surface with points of electrical contact to said semiconductor device having been provided in said second surface of said semiconductor device, said semiconductor device having been provided with a layer of passivation over said second surface of said semiconductor device, openings having been created through said layer of passivation exposing said points of electrical contact to said semiconductor device;

providing a semiconductor device mounting support having a first and a second surface, contact pads having been provided in said first or said second surface of said semiconductor device mounting support;

positioning said semiconductor device over the second surface of said semiconductor device mounting support, said first surface of said semiconductor device facing said second surface of said semiconductor device mounting support;

providing conductive interconnections between said points of electrical contact provided in said second surface of said semiconductor device and contact pads provided over the second surface of said semiconductor device mounting support;

providing an underfill for said semiconductor device;

depositing an interface layer over the surface of said layer of passivation; and

patterning and etching said interface layer, creating at least one opening through said interface layer.

2. The method of claim 1, wherein said interface layer comprising polyimide.

3. The method of claim 1, further comprising depositing a layer of mold compound over the surface of said interface layer, filling said at least one opening created through said interface layer.

4. A method of creating protective layers for the packaging of a semiconductor device, comprising the steps of:

providing a semiconductor device, said semiconductor device having a first and a second surface with points of electrical contact to said semiconductor device having been provided in said second surface of said semiconductor device, said

semiconductor device having been provided with a layer of passivation over said second surface of said semiconductor device, openings having been created through said layer of passivation exposing said points of electrical contact to said semiconductor device;

providing a semiconductor device mounting support having a first and a second surface, contact pads having been provided in said first or said second surface of said semiconductor device mounting support;

positioning said semiconductor device over the second surface of said semiconductor device mounting support, said first surface of said semiconductor device facing said second surface of said semiconductor device mounting support;

providing conductive interconnections between said points of electrical contact provided in said second surface of said semiconductor device and contact pads provided over the second surface of said semiconductor device mounting support;

providing an underfill for said semiconductor device;

depositing an interface layer over the surface of said

layer of passivation;

patterning and etching said interface layer, creating at least one opening through said interface layer; and

depositing a layer of mold compound over the surface of said interface layer, filling said at least one opening created through said interface layer.

5. The method of claim 4, wherein said interface layer comprising polyimide.

6. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor surface;

depositing a stress relief interface layer over said semiconductor surface;

creating at least one opening through said stress relief interface layer; and

depositing a layer of mold compound over the surface of said stress relief interface layer, filling said at least one opening created through said stress relief interface layer.

7. The method of claim 6, said semiconductor surface being a surface of a semiconductor device.

8. The method of claim 6, said stress relief interface layer relieving stress introduced by mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.

9. The method of claim 6, wherein said stress relief interface layer comprising polyimide.

10. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor surface;

depositing a layer of polyimide over the surface of said semiconductor surface;

creating at least one opening through said layer of polyimide; and

depositing a layer of mold compound over the surface of said layer of polyimide, filling said at least one opening created through said layer of polyimide.

11. The method of claim 10, said semiconductor surface being the surface of a semiconductor device.

12. The method of claim 10, wherein said layer of polyimide relieving stress introduced mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.

13. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor device;

depositing a layer of polyimide over a surface of said semiconductor device; and

creating at least one opening through layer of polyimide.

14. The method of claim 13, wherein said layer of polyimide relieving stress introduced by mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.

15. The method of claim 13, further comprising depositing a layer of mold compound over the surface of said layer of polyimide, filling said at least one opening created through layer of polyimide.

16. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor device;

depositing a layer of polyimide over a surface of said semiconductor device;

creating at least one opening through said layer of polyimide; and

depositing a layer of maid compound over the surface of said layer of polyimide, filling said at least one opening created through said layer of polyimide.

17. The method of claim 16, wherein said layer of polyimide relieving stress introduced by mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.