MOS transistor device with a locally maximum concentration region between the source region and the drain region

• US 6,885,062 B2
• Filed: 02/21/2003
• Issued: 04/26/2005
• Est. Priority Date: 02/21/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lantier, Roberta, Hirler, Franz, Zundel, Markus
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US10/371,134
• Publication Number:
  US 20030173618A1
• Time in Patent Office: 795 Days
• Field of Search: 257/330, 257/331, 257/332, 257/333, 257/335, 257/341, 257/E21.419, 257/E29.198, 257/E29.2, 257/E29.201, 257/E29.259, 257/E29.26
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In order to obtain an on resistance that is as low as possible, it is proposed, in the case of a MOS transistor device, to form the avalanche breakdown region in an end region of a trench structure. As an alternative or in addition, it is proposed to form a region of local maximum dopant concentration of a first conductivity type in the region between a source and a drain in proximity to the gate insulation in a manner remote from the gate electrode.

Claims

1. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a given direction;

an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;

a source region having a first conductivity type and formed in said semiconductor region;

a drain region having said first conductivity type and formed in said semiconductor region;

a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure;

an insulation region disposed in said trench structure and insulating said gate electrode device;

a region having a locally maximum dopant concentration of said first conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device;

a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device;

a body reinforcement region of said second conductivity type reinforcing said body region in a direction toward said drain region; and

said drain region having a doping spur, and said region of local maximum dopant concentration of said first conductivity type being disposed in an area of a position located in a transition from one of said body region and said body reinforcement region to said doping spur of said drain region.

2. The MOS transistor device according to claim 1, wherein said avalanche breakdown region includes and is defined by an area of maximum electric field strength.

3. The MOS transistor device according to claim 2, wherein said area of maximum electric field strength is formed between said source region and said drain region in direct proximity to said insulation region and to said region of said trench structure in a manner remote from said gate electrode device.

4. The MOS transistor device according to claim 2, wherein said area of maximum electric field strength is formed between said source region and said drain region in direct proximity to said region of said trench structure and in a manner remote from said gate electrode device.

5. The MOS transistor device according to claim 2, wherein:

said area of maximum electric field strength is formed between said source region and said drain region in direct proximity to said region of said trench structure and remote from said gate electrode device, said area of maximum electrical field strength is further disposed in an area of a space charge zone formed when a breakdown voltage is present between one of said body region and said body reinforcement region and said drain region.

6. The MOS transistor device according to claim 5, wherein said semiconductor region has a lower half and said area of maximum electrical field strength is disposed in said lower half.

7. The MOS transistor device according to claim 1, wherein:

said semiconductor region has a first subregion and a second subregion; and

said trench structure reaches approximately as far as said first subregion of said semiconductor region.

8. The MOS transistor device according to claim 7, further comprising a substrate and said semiconductor region is one of formed in and supported by said substrate, and said trench structure reaches into said substrate.

9. The MOS transistor device according to claim 7, wherein:

said drain region is disposed on a same side of said semiconductor region as said source region and avoids a rear side contact connection of said semiconductor region to a greatest possible extent; and

said first subregion is highly n-doped and formed as a terminal zone in a laterally offset fashion such that said first subregion extends as far as a surface region of one of said semiconductor region and said second subregion.

10. The MOS transistor device according to claim 7, further comprising a substrate and said semiconductor region is one of formed in and supported by said substrate, and said trench structure reaches to said substrate.

11. The MOS transistor device according to claim 1, further comprising a plurality of electrode devices disposed in said trench structure for forming a plurality of gate regions and a plurality of source regions.

12. The MOS transistor device according to claim 1, wherein said body region is disposed in direct proximity to said source region.

13. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a given direction;

an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;

a source region having a given conductivity type and formed in said semiconductor region;

a drain region having said given conductivity type and formed in said semiconductor region;

a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure;

an insulation region disposed in said trench structure and insulating said gate electrode device;

a region having a locally maximum dopant concentration of said given conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device; and

a mesa region formed in said semiconductor region as an intermediate region, said mesa region having in a direction running substantially perpendicular to said given direction a width D_Mesa being lees than a width D_Trench of said trench structure.

14. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a given direction;

an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;

a source region having a given conductivity type and formed in said semiconductor region;

a drain region having said given conductivity type and formed in said semiconductor region;

a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure;

an insulation region disposed in said trench structure and insulating said gate electrode device;

a region having a locally maximum dopant concentration of said given conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device; and

a mesa region formed in said semiconductor region as an intermediate region, said mesa region in a direction running substantially perpendicular to said given direction having a width D_Mesa being less than 2.5 times a maximum thickness D_GOX of said insulation region.

15. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a given direction;

an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;

a source region having a given conductivity type and formed in said semiconductor region;

a drain region having said given conductivity type and formed in said semiconductor region;

a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structures;

an insulation region disposed in said trench structure and insulating said gate electrode device; and

a region having a locally maximum dopant concentration of said given conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device;

said insulation region having a field plate structure resulting in the MOS transistor device being a field plate transistor device.

16. A MOS transistor device, comprising:

a semiconductor region;

a source region having a first conductivity type and formed in said semiconductor region;

a drain region having said first conductivity type and formed in said semiconductor region;

a gate electrode device having an insulation region disposed in-between said source region and said drain region;

a region of local maximum dopant concentration of said first conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device;

a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device;

a body reinforcement region of said second conductivity type reinforcing said body region in a direction toward said drain region; and

said drain region having a doping spur, and said region of local maximum dopant concentration of said first conductivity type being disposed in an area of a position located in a transition from one of said body region and said body reinforcement region and said doping spur of said drain region.

17. The MOS transistor device according to claim 16, wherein said body region is disposed in direct proximity to said source region.

18. The MOS transistor device according to claim 16, wherein:

said semiconductor region has a trench structure formed therein extending substantially in a given direction in said semiconductor region, said gate electrode device is disposed in said trench structure; and

said semiconductor region has an avalanche breakdown region formed in a region of said trench structure selected from the group consisting of an end region of said trench structure, a lower region of said trench structure and a bottom region of said trench structure, resulting in the low on resistance of the MOS transistor device.

19. The MOS transistor device according to claim 18, wherein said avalanche breakdown region includes and is defined by an area of maximum electric field strength.

20. The MOS transistor device according to claim 19, wherein said area of maximum electric field strength is formed between said source region and said drain region in direct proximity to said insulation region and to said region of said trench structure in a manner remote from said gate electrode device.

21. The MOS transistor device according to claim 19, wherein said area of maximum electric field strength is formed between said source region and said drain region in direct proximity to said region of said trench structure and in a manner remote from said gate electrode device.

22. The MOS transistor device according to claim 19,

wherein said area of maximum electric field strength is formed between said source region and said drain region in direct proximity to said region of said trench structure and in a manner remote from said gate electrode device, said area of maximum electrical field strength further disposed in an area of a space charge zone formed when a breakdown voltage is present between one of said body region and said body reinforcement region and said drain region.

23. The MOS transistor device according to claim 22, wherein said semiconductor region has a lower half and said area of maximum electrical field strength is disposed in said lower half.

24. The MOS transistor device according to claim 18, wherein:

said semiconductor region has a first subregion and a second subregion; and

said trench structure reaches approximately as far as said first subregion of said semiconductor region.

25. The MOS transistor device according to claim 24, further comprising a substrate and said semiconductor region is one of formed in and supported by said substrate, and said trench structure reaches into said substrate.

26. The MOS transistor device according to claim 24, wherein:

said drain region is disposed on a same side of said semiconductor region as said source region and avoids a rear side contact connection of said semiconductor region to a greatest possible extent; and

said first subregion is highly n-doped and formed as a terminal zone in a laterally offset fashion such that said first subregion extends as far as a surface region of one of said semiconductor region and said second subregion.

27. The MOS transistor device according to claim 24, further comprising a substrate and said semiconductor region is one of formed in and supported by said substrate, and said trench structure reaches to said substrate.

28. The MOS transistor device according to claim 18, further providing a plurality of electrode devices disposed in said trench structure for forming a plurality of gate regions and a plurality of source regions.

29. A MOS transistor device, comprising:

a semiconductor region;

a source region having a given conductivity type and formed in said semiconductor region;

a drain region having said given conductivity type and formed in said semiconductor region;

a gate electrode device having an insulation region disposed in-between said source region and said drain region;

a region of local maximum dopant concentration of said given conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device; and

a mesa region formed in said semiconductor region as an intermediate region, said mesa region having in a direction running substantially perpendicular to said given direction a width D_Mesa being less than a width D_Trench of said trench structure.

30. A MOS transistor device, comprising:

a semiconductor region;

a source region having a given conductivity type and formed in said semiconductor region;

a drain region having said given conductivity type and formed in said semiconductor region;

a gate electrode device having an insulation region disposed in-between said source region and said drain region;

a region of local maximum dopant concentration of said given conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device; and

a mesa region formed in said semiconductor region as an intermediate region, said mesa region in a direction running substantially perpendicular to said given direction having a width D_Mesa being less than 2.5 times a maximum thickness D_GOX of said insulation region.

31. A MOS transistor device, comprising:

a semiconductor region;

a source region having a given conductivity type and formed in said semiconductor region;

a drain region having said given conductivity type and formed in said semiconductor region;

a gate electrode device having an insulation region disposed in-between said source region and said drain region;

a region of local maximum dopant concentration of said given conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device; and

said insulation region having a field plate structure resulting in the MOS transistor device being a field plate transistor device.

32. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a given direction;

an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device; and

a mesa region formed in said semiconductor region as an intermediate region, said mesa region having, in a direction running substantially perpendicular to said given direction, a width being less than a width of said trench structure.

33. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a given direction;

an insulation region disposed in said trench structure;

an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device; and

a mesa region formed in said semiconductor region as an intermediate region, said mesa region having, in a direction running substantially perpendicular to said given direction, a width being less than 2.5 times a maximum thickness of said insulation region.