MOS transistor device with a locally maximum concentration region between the source region and the drain region
First Claim
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1. A MOS transistor device, comprising:
- a semiconductor region having a trench structure formed therein extending substantially in a given direction;
an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;
a source region having a first conductivity type and formed in said semiconductor region;
a drain region having said first conductivity type and formed in said semiconductor region;
a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure;
an insulation region disposed in said trench structure and insulating said gate electrode device;
a region having a locally maximum dopant concentration of said first conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device;
a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device;
a body reinforcement region of said second conductivity type reinforcing said body region in a direction toward said drain region; and
said drain region having a doping spur, and said region of local maximum dopant concentration of said first conductivity type being disposed in an area of a position located in a transition from one of said body region and said body reinforcement region to said doping spur of said drain region.
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Abstract
In order to obtain an on resistance that is as low as possible, it is proposed, in the case of a MOS transistor device, to form the avalanche breakdown region in an end region of a trench structure. As an alternative or in addition, it is proposed to form a region of local maximum dopant concentration of a first conductivity type in the region between a source and a drain in proximity to the gate insulation in a manner remote from the gate electrode.
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Citations
33 Claims
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1. A MOS transistor device, comprising:
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a semiconductor region having a trench structure formed therein extending substantially in a given direction;
an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;
a source region having a first conductivity type and formed in said semiconductor region;
a drain region having said first conductivity type and formed in said semiconductor region;
a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure;
an insulation region disposed in said trench structure and insulating said gate electrode device;
a region having a locally maximum dopant concentration of said first conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device;
a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device;
a body reinforcement region of said second conductivity type reinforcing said body region in a direction toward said drain region; and
said drain region having a doping spur, and said region of local maximum dopant concentration of said first conductivity type being disposed in an area of a position located in a transition from one of said body region and said body reinforcement region to said doping spur of said drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A MOS transistor device, comprising:
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a semiconductor region having a trench structure formed therein extending substantially in a given direction;
an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;
a source region having a given conductivity type and formed in said semiconductor region;
a drain region having said given conductivity type and formed in said semiconductor region;
a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure;
an insulation region disposed in said trench structure and insulating said gate electrode device;
a region having a locally maximum dopant concentration of said given conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device; and
a mesa region formed in said semiconductor region as an intermediate region, said mesa region having in a direction running substantially perpendicular to said given direction a width DMesa being lees than a width DTrench of said trench structure.
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14. A MOS transistor device, comprising:
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a semiconductor region having a trench structure formed therein extending substantially in a given direction;
an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;
a source region having a given conductivity type and formed in said semiconductor region;
a drain region having said given conductivity type and formed in said semiconductor region;
a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure;
an insulation region disposed in said trench structure and insulating said gate electrode device;
a region having a locally maximum dopant concentration of said given conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device; and
a mesa region formed in said semiconductor region as an intermediate region, said mesa region in a direction running substantially perpendicular to said given direction having a width DMesa being less than 2.5 times a maximum thickness DGOX of said insulation region.
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15. A MOS transistor device, comprising:
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a semiconductor region having a trench structure formed therein extending substantially in a given direction;
an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device;
a source region having a given conductivity type and formed in said semiconductor region;
a drain region having said given conductivity type and formed in said semiconductor region;
a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structures;
an insulation region disposed in said trench structure and insulating said gate electrode device; and
a region having a locally maximum dopant concentration of said given conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device;
said insulation region having a field plate structure resulting in the MOS transistor device being a field plate transistor device.
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16. A MOS transistor device, comprising:
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a semiconductor region;
a source region having a first conductivity type and formed in said semiconductor region;
a drain region having said first conductivity type and formed in said semiconductor region;
a gate electrode device having an insulation region disposed in-between said source region and said drain region;
a region of local maximum dopant concentration of said first conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device;
a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device;
a body reinforcement region of said second conductivity type reinforcing said body region in a direction toward said drain region; and
said drain region having a doping spur, and said region of local maximum dopant concentration of said first conductivity type being disposed in an area of a position located in a transition from one of said body region and said body reinforcement region and said doping spur of said drain region. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A MOS transistor device, comprising:
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a semiconductor region;
a source region having a given conductivity type and formed in said semiconductor region;
a drain region having said given conductivity type and formed in said semiconductor region;
a gate electrode device having an insulation region disposed in-between said source region and said drain region;
a region of local maximum dopant concentration of said given conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device; and
a mesa region formed in said semiconductor region as an intermediate region, said mesa region having in a direction running substantially perpendicular to said given direction a width DMesa being less than a width DTrench of said trench structure.
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30. A MOS transistor device, comprising:
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a semiconductor region;
a source region having a given conductivity type and formed in said semiconductor region;
a drain region having said given conductivity type and formed in said semiconductor region;
a gate electrode device having an insulation region disposed in-between said source region and said drain region;
a region of local maximum dopant concentration of said given conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device; and
a mesa region formed in said semiconductor region as an intermediate region, said mesa region in a direction running substantially perpendicular to said given direction having a width DMesa being less than 2.5 times a maximum thickness DGOX of said insulation region.
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31. A MOS transistor device, comprising:
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a semiconductor region;
a source region having a given conductivity type and formed in said semiconductor region;
a drain region having said given conductivity type and formed in said semiconductor region;
a gate electrode device having an insulation region disposed in-between said source region and said drain region;
a region of local maximum dopant concentration of said given conductivity disposed substantially between said source region and said drain region in direct proximity to said insulation region in a manner remote from said gate electrode device resulting in a low on resistance of the MOS transistor device; and
said insulation region having a field plate structure resulting in the MOS transistor device being a field plate transistor device.
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32. A MOS transistor device, comprising:
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a semiconductor region having a trench structure formed therein extending substantially in a given direction;
an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device; and
a mesa region formed in said semiconductor region as an intermediate region, said mesa region having, in a direction running substantially perpendicular to said given direction, a width being less than a width of said trench structure.
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33. A MOS transistor device, comprising:
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a semiconductor region having a trench structure formed therein extending substantially in a given direction;
an insulation region disposed in said trench structure;
an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device; and
a mesa region formed in said semiconductor region as an intermediate region, said mesa region having, in a direction running substantially perpendicular to said given direction, a width being less than 2.5 times a maximum thickness of said insulation region.
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Specification