Fixed frequency hysteretic regulator

• US 6,885,175 B2
• Filed: 10/24/2003
• Issued: 04/26/2005
• Est. Priority Date: 10/25/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Mihalka, Alex
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US10/693,701
• Publication Number:
  US 20040135563A1
• Time in Patent Office: 550 Days
• Field of Search: 323/280, 323/282, 323/283, 323/284, 323/351
• US Class Current: 323/282
• CPC Class Codes: G05F 1/40 using discharge tubes or semiconductor devices as final control devices
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit

Abstract

A control circuit for controlling a hysteretic regulator to operate at substantially fixed frequency has a voltage offset circuit which receives a first feedback signal and generates a pair of upper and lower offset voltages; a control reference stage which receives a reference voltage and the upper and lower offset voltages and outputs upper and lower control reference voltages; and a window comparator which receives the upper and lower control reference voltages and an output voltage feedback signal and outputs a pair of upper and lower control voltages for controlling switching of the hysteretic regulator at a fixed frequency. The first feedback signal may be representative of a switching frequency, a temperature or an output voltage of the hysteretic regulator, for example. The voltage offset circuit may further receive a second and/or an additional feedback signal. The first, second and/or additional feedback signals further may be weighted. According to particularly useful embodiments of the invention, the control method for a hysteretic regulator may use both output voltage and switching frequency as primary feedback signals, thereby allowing the window limits (control voltages) to be positioned completely independently and in any possible configuration about the nominal voltage. In other words, the two window limits can be positioned symmetrically or asymmetrically about the nominal voltage, and at the same time the lower window limit can be positioned either below, above, or equal to the upper window limit.

Claims

1. A control circuit for controlling a hysteretic regulator to operate at substantially fixed frequency, comprising:

a voltage offset circuit which receives a switching frequency feedback signal and an output voltage feedback signal from said hysteretic regulator and generates a pair of upper and lower offset voltages;

a control reference stage which receives a reference voltage and said upper and lower offset voltages and outputs upper and lower control reference voltages; and

a window comparator which receives said upper and lower control reference voltages and said output voltage feedback signal and outputs a pair of upper and lower control voltages for controlling switching of said hysteretic regulator at a fixed frequency.

2. A control circuit as set forth in claim 1, wherein said control reference stage comprises a first summer which receives said reference voltage and said upper offset voltage, and a second summer which receives said reference voltage and said lower offset voltage;

and said first and second summers respectively output said upper and lower control reference voltages.

3. A control circuit as set forth in claim 2, wherein said first summer adds said upper offset voltage to said reference voltage, and said second summer subtracts said lower offset voltage from said reference voltage.

4. A control circuit as set forth in claim 1, wherein said voltage offset circuit comprises a frequency/voltage converter which receives said frequency feedback signal.

5. A control circuit as set forth in claim 4, wherein said voltage offset circuit further comprises an error amplifier in series with said frequency/voltage converter.

6. A control circuit as set forth in claim 5, further comprising an output filter in series with said error amplifier.

7. A control circuit as set forth in claim 4, further comprising an output filter in series with said frequency/voltage converter.

8. A control circuit as set forth in claim 4, further comprising a resistive network connected to said voltage offset circuit for delivering said upper and lower offset voltages to said control reference stage.

9. A control circuit as set forth in claim 8, wherein said resistive network further delivers said reference voltage to said control reference stage.

10. A control circuit as claimed in claim 1, wherein said upper and lower control voltages are positioned symmetrically about a nominal voltage.

11. A control circuit as claimed in claim 1, wherein said upper and lower control voltages are positioned asymmetrically about a nominal voltage.

12. A control circuit as claimed in claim 1, wherein said upper control voltage is positioned higher than said lower control voltage.

13. A control circuit as claimed in claim 12, wherein said upper and lower control voltages are positioned asymmetrically about a nominal voltage.

14. A control circuit as claimed in claim 1, wherein said upper control voltage is positioned lower than said lower control voltage.

15. A control circuit as claimed in claim 14, wherein said upper and lower control voltages are positioned asymmetrically about a nominal voltage.

16. A control circuit as claimed in claim 1, wherein at least one of said upper and lower control voltages is positioned above a nominal voltage.

17. A control circuit as claimed in claim 16, wherein both of said upper and lower control voltages are positioned above said nominal voltage.

18. A control circuit as claimed in claim 1, wherein both of said upper and lower control voltages are positioned below said nominal voltage.

19. A control circuit as claimed in claim 1, wherein said upper and lower control voltages are substantially equal.

20. A control circuit as claimed in claim 10, wherein said upper and lower control voltages are substantially equal.

21. A control circuit for controlling a hysteretic regulator to operate at substantially fixed frequency, comprising:

a voltage offset circuit which receives a first feedback signal and generates a pair of upper and lower offset voltages;

a control reference stage which receives a reference voltage and said upper and lower offset voltages and outputs upper and lower control reference voltages; and

a window comparator which receives said upper and lower control reference voltages and an output voltage feedback signal and outputs a pair of upper and lower control voltages for controlling switching of said hysteretic regulator at a fixed frequency.

22. A control circuit as claimed in claim 21, wherein said first feedback signal is representative of a switching frequency of said hysteretic regulator.

23. A control circuit as claimed in claim 21, wherein said first feedback signal is representative of a temperature of said hysteretic regulator.

24. A control circuit as claimed in claim 21, wherein said voltage offset circuit further receives a second feedback signal.

25. A control circuit as claimed in claim 24, wherein said first and second feedback signals are representative of a switching frequency and a temperature of said hysteretic regulator, respectively.

26. A control circuit as claimed in claim 24, wherein said voltage offset circuit further comprises a circuit for weighting said first and second feedback signals.

27. A control circuit as claimed in claim 24, wherein said second feedback signal is said output voltage feedback signal.

28. A control circuit as claimed in claim 27, wherein said voltage offset circuit further comprises a circuit for weighting said first arid second feedback signals.

29. A control circuit as claimed in claim 24, wherein said voltage offset circuit further receives at least one additional feedback signal.

30. A control circuit as claimed in claim 29, wherein said voltage offset circuit further comprises a circuit for weighting said first, said second, and said additional feedback signals.