Multi-track integrated spiral inductor

• US 6,885,275 B1
• Filed: 01/28/2000
• Issued: 04/26/2005
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chang, James Y. C.
• Primary Examiner(s): DONOVAN, LINCOLN D
• Application Number:
  US09/493,942
• Time in Patent Office: 1,915 Days
• Field of Search: 336/200, 336/223, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated circuit inductor includes a spiral pattern disposed upon a substrate. The track of the spiral is divided into multiple tracks to form a multi-track inductor. The individual tracks are disposed side by side and in different layers. Tracks that are aligned vertically are coupled by feed throughs, or vias. Multiple vias are used along the length of each of the multiple tracks. Tracks disposed in the same layer are joined together at their beginning, and at their termination. A patterned shield is fabricated from conductive fingers of n+ salicided material that is separated by non conducting polysilicon that fills the gaps between the fingers. The conductive fingers are coupled together in groups, which are in turn tied to a single point ground. In tying the groups together, a gap in the conducting path is provided to prevent ground loop currents. The shield is disposed between the multi-track inductor and the substrate.

Claims

1. An integrated circuit inductor comprising:

a substrate;

a spiral inductor metalization pattern disposed on the substrate including a plurality of parallel tracks in a spiral pattern each track having a first end and a second end and having the first ends coupled together and the second ends coupled together; and

a n+ diffusion layer disposed in the substrate directly underneath the spiral inductor metalization pattern;

the n⁺ diffusion layer has a fingered pattern shape with n+ fingers electrically isolated by regions of polysilicon.

2. The integrated circuit inductor of claim 1, wherein the substrate is fabricated utilizing a CMOS process.

3. The integrated circuit inductor of claim 1, wherein the spiral inductor is a square configuration.

4. The integrated circuit inductor of claim 1, wherein the spiral inductor is a octagonal configuration.

5. The integrated circuit inductor of claim 1, in which the plurality of tracks are disposed in a common layer of the substrate.

6. The integrated circuit inductor of claim 1, in which the plurality of tracks are disposed in different layers of the substrate.

7. The integrated circuit inductor of claim 1, in which the plurality of tracks are disposed in different layers of the substrate and coupled together with a via.

8. The integrated circuit inductor of claim 1, in which the fingered pattern is coupled to a common ground reference.

9. The integrated circuit inductor of claim 8, in which the n⁺ diffusion layer further comprises a second fingered pattern coupled to the common ground reference by a conductive strip that does not provide a ground loop path.

10. An integrated circuit inductor comprising:

a substrate having a first layer and a second layer;

a first track disposed on the first layer in a first spiral pattern and having a first input and a first output;

a second track disposed on the second layer in a second spiral pattern and having a second input and a second output, the second spiral pattern oriented parallel to the first spiral pattern; and

a pattern of via holes sufficient to couple a varying voltage present along the length of the first track on to the second track;

the first and second inputs connected together by a first via hole of the pattern of via holes, and the first and second outputs connected together by a second via hole of the pattern of via holes;

said first track and said second track operating in parallel from said first and second inputs to said first and second outputs.

11. An integrated circuit inductor, comprising:

a substrate having a first layer and a second layer;

a first spiral pattern disposed on the first layer of the substrate and having a first end and a second end;

a second spiral pattern disposed on the second layer of the substrate and oriented parallel to the first spiral pattern, and having a first end and a second end; and

the first end of the a first spiral pattern connected to the first end of the second spiral pattern and forming an input for the integrated circuit inductor, and the second end of the first spiral pattern connected to the second end of the second spiral pattern and forming an output for the integrated circuit inductor

said first spiral pattern and said second spiral pattern operating in parallel from said input to said output.

12. The integrated circuit inductor of claim 11, further comprising a plurality of via holes disposed along a length of the first spiral pattern and connected to the second spiral pattern.

13. The integrated circuit inductor of claim 11, further comprising a n+ diffusion layer disposed in the substrate beneath the first spiral pattern and the second spiral pattern.

14. The integrated circuit inductor of claim 13, wherein the n+ diffusion layer is formed in a fingered pattern from n+ material having n+ fingers electrically isolated by regions of polysilicon to produce the fingered pattern.

15. The integrated inductor of claim 11, wherein the substrate is a CMOS substrate.