Dynamic data restore in thyristor-based memory device

• US 6,885,581 B2
• Filed: 04/05/2002
• Issued: 04/26/2005
• Est. Priority Date: 04/05/2001
• Status: Expired due to Fees

• Current Assignee: T-Ram, LLC
• Original Assignee: T-Ram, Inc.
• Inventors: Nemati, Farid, Cho, Hyun-jin, Igehy, Robert Homan
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/472,737
• Publication Number:
  US 20040104400A1
• Time in Patent Office: 1,117 Days
• Field of Search: 365/159, 365/71, 365/100, 365/148, 365/174, 365/222
• US Class Current: 365/159
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT

Abstract

A dynamically-operating restoration circuit (106) is used to apply a voltage or current restore pulse signal to thyristor-based memory cells (108) and therein restore data in the cell using the internal positive feedback loop of the thyristor (110). In one example implementation, the internal positive feedback loop in the thyristor (110) is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Claims

1. An electronic circuit arrangement, comprising:

a plurality of memory cells, each memory cell having a thyristor with an internal positive feedback loop; and

a restoration circuit adapted to apply a restore pulse to each memory cell and therein restore data in the cell using the internal positive feedback loop of the thyristor.

2. The electronic circuit arrangement of claim 1, wherein each memory cell has a binary state prior to restoration and wherein the restoration circuit is not dependent on said binary state.

3. The electronic circuit arrangement of claim 1, wherein the thyristor has a holding current threshold and wherein application of the restore pulse results in current in the thyristor having a time average that is smaller than the holding current threshold of the thyristor.

4. The electronic circuit arrangement of claim 1, wherein the thyristor has a holding current threshold and wherein application of the restore pulse results in a thyristor current having a time average that is at least as large as the holding current threshold of the thyristor.

5. The electronic circuit arrangement of claim 1, wherein the restore pulse is controlled to track variations in a specific characteristic of the memory cells.

6. The electronic circuit arrangement of claim 5, wherein the specific characteristic of the memory cells is temperature.

7. The electronic circuit arrangement of claim 1, further including means for controlling and maintaining the restore pulse for a sufficient duration.

8. The electronic circuit arrangement of claim 1, further including means for controlling and maintaining the restore pulse above a threshold.

9. The electronic circuit arrangement of claim 1, wherein the restoration pulse is applied during a memory-access cycle.

10. The electronic circuit arrangement of claim 1, wherein the thyristor has a holding current threshold and wherein the restoration circuit is further adapted to apply the restore pulse during a limited time period in which the thyristor can be restored into the forward conducting state after current passing through the thyristor is removed from the device, the current passing through the thyristor being at least equal to the holding current threshold.

11. A method for dynamically restoring data in a thyristor-based memory device having a plurality of memory cells, each memory cell having a thyristor with an internal positive feedback loop, the method comprising:

periodically applying a restore pulse for a short interval to each memory cell and therein restoring data in the cell using the internal positive feedback loop of the thyristor.

12. The method of claim 11, and not including use of an external sense circuit to determine the content of the memory cell prior to restoration.

13. The method of claim 11, wherein the thyristor has a holding current threshold and wherein application of the restore pulse results in current in the thyristor having a time average that is smaller than the holding current threshold of the thyristor.

14. The method of claim 11, wherein the thyristor has a holding current threshold and wherein application of the restore pulse results in current in the thyristor having a time average that is at least as large as the holding current threshold of the thyristor.

15. The method of claim 11, further including controlling the restore pulse to track variations in a specific characteristic of the memory cells.

16. The method of claim 11, further including controlling the restore pulse to track temperature variations of the memory cells.

17. The method of claim 11, wherein the step of periodically applying includes providing the restore pulse as part of a periodic waveform, and further including controlling the periodic waveform to track variations in a specific characteristic of the memory cells.

18. The method of claim 17, wherein the specific characteristic is temperature.

19. The method of claim 11, wherein the step of periodically applying includes:

monitoring at least one characteristic of a representative memory cell;

providing the restore pulse as part of a periodic waveform; and

, in response to said step of monitoring, controlling the periodic waveform to adjust a characteristic of the periodic waveform.

20. The method of claim 11, further including providing a cycle dedicated for applying the restore pulse.

21. The method of claim 11, wherein the plurality of memory cells are arranged in an array defined by bit-line and word-line axes, and where the step of periodically applying includes pulsing selected memory cells by pulsing along one of the axes at the end of at least one type of access cycle.

22. The method of claim 21, wherein said at least one type of access cycle is only one of:

a memory read cycle; and

a memory write cycle.

23. The method of claim 11, further including presenting the restoration pulse as part of a memory read/write cycle.

24. A method for maintaining a forward conducting state of a thyristor-based memory device, the method comprising:

during a limited time period in which the thyristor can be restored into the forward conducting state after a holding current passing through the thyristor is removed, applying a pulse to the thyristor, the pulse being adapted to maintain the forward conducting state of the thyristor.

25. The method of claim 24, wherein the pulse is presented periodically, each pulse lasting less than the limited time period.

26. A method for dynamically restoring data in a memory device having a plurality of memory cell arrays and each memory cell having an internal positive feedback loop, the method comprising:

periodically applying a restore pulse for a short interval to each memory cell, the periodically-applied pulse being adapted to restore a forward conducting state of an element in the memory cell in response to the internal positive feedback loop.

27. The method of claim 26, wherein the element in the memory cell is a thyristor.

28. The method of claim 26, not including use of an external sense circuit to determine the content of the memory cell prior to restoration.

29. An electronic circuit arrangement, comprising:

a plurality of memory cells, each memory cell having a thyristor with an internal positive feedback loop; and

thyristor-state restoration means for periodically applying a restore pulse for a short interval to each memory cell and therein restoring data in the cell using the internal positive feedback loop of the thyristor.

30. An electronic circuit arrangement, comprising:

an array of memory cells, each memory cell having an access circuit and a thyristor with a capacitively-coupled gate and an internal positive feedback loop, the access circuit being electrically coupled to the thyristor and being controlled to provide a current path for the thyristor;

an array-control circuit electrically coupled to each access circuit and adapted both to control data access for each memory cell and to enable and disable the current path provided by each access circuit; and

a restoration circuit adapted to apply a restore pulse, after the current path is disabled, to the access circuit of each memory cell, application of the restore pulse resulting in current flowing through the current path and the thyristor for the memory cell and in using the internal positive feedback loop of the thyristor to restore data in the cell.