Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device

• US 6,885,599 B2
• Filed: 01/27/2004
• Issued: 04/26/2005
• Est. Priority Date: 07/19/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Sonoda, Takahiro, Morita, Sadayuki, Saitoh, Yoshikazu
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/764,539
• Publication Number:
  US 20040184344A1
• Time in Patent Office: 455 Days
• Field of Search: 365/201, 365/63, 365/185.09, 324/756, 324/757, 324/758, 324/765, 324/538
• US Class Current: 365/201
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

Claims

1. A method of manufacturing a semiconductor device, comprising:

producing a first semiconductor wafer including first semiconductor chips;

producing a second semiconductor wafer including second semiconductor chips;

performing burn-in of the first and the second semiconductor wafer;

cutting the first and second semiconductor wafers to produce a batch of first semiconductor chips and a batch of second semiconductor chips, respectively, and

assembling one of the first semiconductor chips and one of the second semiconductor chips to produce the semiconductor device,

wherein assembling includes a process of forming a stacked arrangement of one or more of the first semiconductor chips and one or more of the second semiconductor chips on a substrate to produce the semiconductor device and providing prescribed electrical connections therebetween.

2. The method of manufacturing a semiconductor device according to claim 1,

wherein performance of the burn-in comprises:

performing a contact check for judging electric connection/non-connection between each needle connected to a test apparatus and each terminal provided in each of the first and second semiconductor chips of the first and second semiconductor wafers, and

wherein each of the first semiconductor chips includes a volatile memory and each of the second chips involves a nonvolatile memory.

3. The method of manufacturing a semiconductor device according to claim 1,

wherein performance of the burn-in comprises:

performing a contact check for judging electric connection/non-connection between each needle connected to a test apparatus and each terminal provided in each of the first and second semiconductor chips of the first and second semiconductor wafers, and

wherein the substrate is a wiring substrate.

4. A method of manufacturing a semiconductor device, comprising:

producing a first semiconductor wafer including first semiconductor chips;

producing a second semiconductor wafer including second semiconductor chips;

performing burn-in of the first and the second semiconductor wafer;

cutting the first and second semiconductor wafers to produce a batch of first semiconductor chips and a batch of second semiconductor chips, respectively, and

assembling one of the first semiconductor chips and one of the second semiconductor chips to produce the semiconductor device,

wherein assembling includes a process of forming a stacked arrangement of one or more of the first semiconductor chips and one or more of the second semiconductor chips on a substrate to produce the semiconductor device and providing prescribed electrical connections therebetween, and

wherein the substrate is a wiring substrate.

5. The method of manufacturing a semiconductor device according to claim 4,

wherein performance of the bum-in comprises:

performing a contact check for judging electric connection/non-connection between each needle connected to a test apparatus and each terminal provided in each of the first and second semiconductor chips of the first and second semiconductor wafers, and

wherein each of the first semiconductor chips includes a volatile memory and each of the second chips involves a nonvolatile memory.

6. A method of manufacturing a semiconductor, comprising:

producing a first semiconductor wafer including first semiconductor chips;

producing a second semiconductor wafer including second semiconductor chips;

performing burn-in of the first and the second semiconductor wafer;

cutting the first and second semiconductor wafers to produce a batch of first semiconductor chips and a batch of second semiconductor chips, respectively, and

assembling one of the first semiconductor chips and one of the second semiconductor chips to produce the semiconductor device,

wherein assembling includes a process of forming a stacked arrangement of one or more of the first semiconductor chips and one or more of the second semiconductor chips on a substrate to produce the semiconductor device and providing prescribed electrical connections therebetween, and

wherein each of the first semiconductor chips includes a volatile memory and each of the second chips includes a nonvolatile memory.