Shift-register circuit

• US 6,885,723 B2
• Filed: 04/02/2003
• Issued: 04/26/2005
• Est. Priority Date: 08/13/2002
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Yu, Jian-Shen
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US10/406,063
• Publication Number:
  US 20040032926A1
• Time in Patent Office: 755 Days
• Field of Search: 377/78, 377/79, 377/81
• US Class Current: 377/78
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift-register circuit. The PMOS transistor includes a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first drain, a third drain coupled to the inverse clock signal, and a third source. The third NMOS transistor includes a fourth gate coupled to the first gate, a fourth drain coupled to the second gate, and a fourth source. The fourth NMOS transistor includes a fifth gate coupled to the first source, a fifth drain coupled to the second source, and a fifth source coupled to the ground voltage level. The fifth NMOS transistor having a sixth gate coupled to the third source, a sixth drain coupled to the fourth source, and a sixth source coupled to the ground voltage level. The first inverter acts as an inverse output terminal and is coupled to the second source for outputting an inverse output signal. The second inverter acts as an output terminal and is coupled to the first inverter for outputting an output signal.

Claims

1. A shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, an inverse clock signal, and a ground voltage level, comprising:

a PMOS transistor having a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit;

a first NMOS transistor having a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source;

a capacitor coupled between the second gate and the second source;

a second NMOS transistor having a third gate coupled to the first drain, a third drain coupled to the inverse clock signal, and a third source;

a third NMOS transistor having a fourth gate coupled to the first source, a fourth drain coupled to the second source, and a fourth source coupled to the ground voltage level;

a fourth NMOS transistor having a fifth gate coupled to the first gate, a fifth drain coupled to the third source, and a fifth source;

a fifth NMOS transistor having a sixth gate coupled to the first source, a sixth drain coupled to the fifth source, and a sixth source coupled to the ground voltage level;

a sixth NMOS transistor having a seventh gate coupled to the sixth drain, a seventh drain coupled to the second gate, and a seventh source coupled to the ground voltage level;

a seventh NMOS transistor having an eighth gate coupled to the sixth drain, an eighth drain coupled to the second source, and an eighth source coupled to the ground voltage level;

a first inverter acting as an inverse output terminal coupled to the eighth drain for outputting an inverse output signal; and

a second inverter acting as an output terminal coupled to the first inverter for outputting an output signal.

2. The shift-register circuit as claimed in claim 1, wherein the NMOS and PMOS transistors are thin film transistors.

3. The shift-register circuit as claimed in claim 1, wherein the capacitor is a MOS capacitor.

4. The shift-register circuit as claimed in claim 1, wherein the first and second inverters are CMOS inverters.

5. A shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, an inverse clock signal, and a ground voltage level, comprising:

a PMOS transistor having a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit;

a first NMOS transistor having a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source;

a capacitor coupled between the second gate and the second source;

a second NMOS transistor having a third gate coupled to the first drain, a third drain coupled to the inverse clock signal, and a third source;

a third NMOS transistor having a fourth gate coupled to the first gate, a fourth drain coupled to the second gate, and a fourth source;

a fourth NMOS transistor having a fifth gate coupled to the first source, a fifth drain coupled to the second source, and a fifth source coupled to the ground voltage level;

a fifth NMOS transistor having a sixth gate coupled to the third source, a sixth drain coupled to the fourth source, and a sixth source coupled to the ground voltage level;

a first inverter acting as an inverse output terminal coupled to the second source for outputting an inverse output signal; and

a second inverter acting as an output terminal coupled to the first inverter for outputting an output signal.

6. The shift-register circuit as claimed in claim 5, wherein the NMOS and PMOS transistors are thin film transistors.

7. The shift-register circuit as claimed in claim 5, wherein the capacitor is a MOS capacitor.

8. The shift-register circuit as claimed in claim 5, wherein the first and second inverters are CMOS inverters.