×

Shift-register circuit

  • US 6,885,723 B2
  • Filed: 04/02/2003
  • Issued: 04/26/2005
  • Est. Priority Date: 08/13/2002
  • Status: Active Grant
First Claim
Patent Images

1. A shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, an inverse clock signal, and a ground voltage level, comprising:

  • a PMOS transistor having a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit;

    a first NMOS transistor having a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source;

    a capacitor coupled between the second gate and the second source;

    a second NMOS transistor having a third gate coupled to the first drain, a third drain coupled to the inverse clock signal, and a third source;

    a third NMOS transistor having a fourth gate coupled to the first source, a fourth drain coupled to the second source, and a fourth source coupled to the ground voltage level;

    a fourth NMOS transistor having a fifth gate coupled to the first gate, a fifth drain coupled to the third source, and a fifth source;

    a fifth NMOS transistor having a sixth gate coupled to the first source, a sixth drain coupled to the fifth source, and a sixth source coupled to the ground voltage level;

    a sixth NMOS transistor having a seventh gate coupled to the sixth drain, a seventh drain coupled to the second gate, and a seventh source coupled to the ground voltage level;

    a seventh NMOS transistor having an eighth gate coupled to the sixth drain, an eighth drain coupled to the second source, and an eighth source coupled to the ground voltage level;

    a first inverter acting as an inverse output terminal coupled to the eighth drain for outputting an inverse output signal; and

    a second inverter acting as an output terminal coupled to the first inverter for outputting an output signal.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×