High speed methods for maintaining a summary of thread activity for multiprocessor computer systems
First Claim
1. In a multiprocessor computer system having multiple interconnected processing nodes cach with one or more processors and physical memory, a data structure for storing execution history data indicating of states of threads that are used for providing mutual exclusion between current and next generation data elements, comprising:
- a first level bit mask stored in physical memory accessibe to all nodes and containing a bit per node, the bit indicating whether the corresponding nodes contains a processor that has not yet passed through a quiescent state; and
a second level bit mask stored in the physical memory of each processing node and containing a bit per processor associated with a particular node identified in the first level bit mask, the bit indicating whether the corresponding processor has not yet passed through a quiescent state.
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Abstract
A high-speed method for maintaining a summary of thread activity reduces the number of remote-memory operations for an n processor, multiple node computer system from n2 to (2n−1) operations. The method uses a hierarchical summary of-thread-activity data structure that includes structures such as first and second level bit masks. The first level bit mask is accessible to all nodes and contains a bit per node, the bit indicating whether the corresponding node contains a processor that has not yet passed through a quiescent state. The second level bit mask is local to each node and contains a bit per processor per node, the bit indicating whether the corresponding processor has not yet passed through a quiescent state. The method includes determining from a data structure on the processor'"'"'s node (such as a second level bitmask) if the processor has passed through a quiescent state. If so, it is then determined from the data structure if all other processors on its node have passed through a quiescent state. If so, it is then indicated in a data structure accessible to all nodes (such as the first level bitmask) that all processors on the processor'"'"'s node have passed through a quiescent state. The local generation number can also be stored in the data structure accessible to all nodes. If a processor determines from this data structure that the processor is the last processor to pass through a quiescent state, the processor updates the data structure for storing a number of the current generation stored in the memory of each node.
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Citations
10 Claims
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1. In a multiprocessor computer system having multiple interconnected processing nodes cach with one or more processors and physical memory, a data structure for storing execution history data indicating of states of threads that are used for providing mutual exclusion between current and next generation data elements, comprising:
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a first level bit mask stored in physical memory accessibe to all nodes and containing a bit per node, the bit indicating whether the corresponding nodes contains a processor that has not yet passed through a quiescent state; and
a second level bit mask stored in the physical memory of each processing node and containing a bit per processor associated with a particular node identified in the first level bit mask, the bit indicating whether the corresponding processor has not yet passed through a quiescent state.
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2. In a multiprocessor computer system having multiple interconnected processing nodes each with one or more processors and physical memory, a data structure stored in the physical memory on each node for storing a number of the current generation of data elements being processed by a processor on a node, the data structure comprising a variable stored in the physical memory of each node and containing the current generation number, wherein the current generation number on the nodes are updated in lockstep so that the nodes have local access to copies of the current generation number.
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3. In a multiprocessor computer system having multiple interconnected processing nodes each with one or more processors and physical memory, a method for a processor to maintain a summary of thread activity as part of a method for providing mutual exclusion between current and next generation data elements, comprising:
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determining from a first data structure on the processor'"'"'s node if the processor has passed through a quiescent state;
if so, determining from a second data structure on the processor'"'"'s node if all other processors on its node have passed through a quiescent state; and
if so, indicating in a third data structure accessible to all nodes that all processors on the processor'"'"'s node have passed through a quiescent state. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10)
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Specification