Multiple oxide thicknesses for merged memory and logic applications
First Claim
1. A method comprising:
- forming a top layer of SiO2 on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation, such that the top layer has a top thickness; and
forming a trench layer of SiO2 on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness.
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Abstract
Methods are provided for fabricating multiple oxide thicknesses on a single silicon wafer. Methods are provided to form multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. These methods can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Methods for forming a semiconductor device include forming a top layer of SiO2 on a top surface of a silicon wafer. A trench layer of SiO2 is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO2 are such that a thickness of the top layer is different from a thickness of the trench layer.
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Citations
44 Claims
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1. A method comprising:
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forming a top layer of SiO2 on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation, such that the top layer has a top thickness; and
forming a trench layer of SiO2 on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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10. A method comprising:
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forming a top device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and the top device includes a top gate separated from the top surface by a top gate oxide; and
forming a trench device on a trench wall of a trench in the silicon wafer, wherein the trench wall has a (110) crystal plane orientation and the trench device includes a trench gate separated from the trench wall by a trench gate oxide, such that a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method comprising:
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forming a top device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and wherein the top device includes a top gate separated from the top surface by a thermally formed top gate oxide;
forming a trench in the silicon wafer such that a trench wall forms with a (110) crystal plane orientation; and
forming a trench device on the trench wall, the trench device including a trench gate separated from the trench wall by a thermally formed trench gate oxide, wherein the top gate oxide has a thickness which is different from a thickness of the trench gate oxide. - View Dependent Claims (17, 18, 19, 20)
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21. A method comprising:
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forming a top layer of SiO2 on a top surface of a silicon wafer, wherein the top surface has a (111) crystal plane orientation, such that the top layer has a top thickness; and
forming a trench layer of SiO2 on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer. - View Dependent Claims (22, 23, 24, 25)
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26. A method comprising:
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forming a top surface of a silicon wafer with a (111) crystalline plane orientation;
forming a trench in the silicon wafer, wherein a trench wall has a (110) crystalline plane orientation; and
simultaneously forming a top oxide layer on the top surface and forming a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer. - View Dependent Claims (27, 28, 29)
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30. A method comprising:
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forming a top layer of SiO2 on a top surface of a silicon wafer, wherein the top surface has a (111) crystalline orientation, such that the top layer has a top thickness; and
forming a trench layer of SiO2 on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystalline orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer, wherein forming the top layer of SiO2 and forming the trench layer of SiO2 includes forming the top layer of SiO2 and forming the trench layer of SiO2 simultaneously during a linear growth period, and wherein forming the trench layer of SiO2 on the trench wall includes forming the trench layer of SiO2 that has a thickness that is approximately 30% thicker than a thickness of the top layer of SiO2. - View Dependent Claims (31, 32)
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33. A method comprising:
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forming a logic device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and wherein the logic device includes a logic gate separated from the top surface by a logic gate oxide; and
forming an EEPROM (Electronically Erasable Programmable Read Only Memory) device on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface and wherein the EEPROM device includes an EEPROM gate separated from the trench wall by an EEPROM gate oxide, wherein the logic gate oxide has a thickness which is different from a thickness of the EEPROM gate oxide. - View Dependent Claims (34)
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Specification