Optimization methods for on-chip interconnect geometries suitable for ultra deep sub-micron processes

• US 6,887,791 B2
• Filed: 12/19/2002
• Issued: 05/03/2005
• Est. Priority Date: 06/06/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Jung, Won-Young
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US10/327,308
• Publication Number:
  US 20030228757A1
• Time in Patent Office: 866 Days
• Field of Search: 438/689, 438/714, 438/717, 438/737, 438/738, 438/761
• US Class Current: 438/689
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted interconnect process parameters but also the input of LPE (Layout Parasitic Extraction) tools in physical verification stage.

Claims

1. A method of establishing a set of parameter values for use in simulating the operation of an integrated circuit, the integrated circuit being formed of a structure comprising a conductive layer formed upon a substrate and a plurality of interconnect layers formed over the conductive layer, and including inter-layer and intra-layer dielectrics and a dielectric layer over the topmost of the interconnect layers, the method including:

for a first portion of the structure, characterized by a first subset of the parameters and including a first of said layers and a second layer adjacent to the first layer, optimizing the first portion of the structure to establish values for the first subset of the parameters; and

for a second portion of the structure, characterized by a second subset of parameters and including the second of said layers and a third layer adjacent the second layer and distinct from the first, subsequently optimizing the second portion of the structure to establish values for the second subset, wherein the first and second subset share one or more of the parameters and the second subset is optimized holding the previously established values for the first subset fixed.

2. The method of claim 1, wherein said first layer is a polysilicon layer and said second layer is the adjacent interconnect layer, and wherein the first portion of the structure further includes the substrate and the dielectric region intermediate between the substrate and the poly layer.

3. The method of claim 1, wherein said first layer is the topmost of the interconnect layers and said second layer is the adjacent interconnect layer below the topmost of the interconnect layers.

4. The method of claim 1, wherein said dielectric layer over the topmost of the interconnect layers is a conformal structure.

5. The method of claim 1, wherein said dielectric layer over the topmost of the interconnect layers is a planar structure.

6. The method of claim 1, wherein said method is performed as a semi-automatic process.

7. The method of claim 1, wherein said method is performed as a manual process.

8. The method of claim 1, wherein the first portion of the structure further includes a fourth layer adjacent to the first layer and distinct from the first, second, and third layers.

9. The method of claim 1, wherein the second portion of the structure further includes a fourth layer adjacent to the first layer and distinct from the first, second, and third layers.

10. The method of claim 9, wherein the first portion of the structure further includes a fifth layer adjacent to the first layer and distinct from the first, second, third, and fourth layers.

11. The method of claim 1, further comprising:

subsequent to said optimizing the second portion of the structure, re-optimizing the combined first and second portions of the structure to refine the set of parameter values.

12. The method of claim 1, wherein one or more of said interconnect layers is a multi-conductor layer.

13. The method of claim 12, wherein said multi-conductor layer is copper damascene layer.

14. The method of claim 1, wherein one or more of said dielectrics form an anisotropic dielectric structure.

15. The method of claim 1, wherein one or more of said inter-layer dielectrics is a multi-layer dielectric.

16. The method of claim 1, wherein said set of parameter values are used for forming an interconnect process technology file.

17. The method of claim 16, wherein the interconnect process technology file is for interfacing to electronic design automation (EDA) tools.

18. The method of claim 1, wherein one or more of said dielectrics comprise multiple layers.

19. The method of claim 18, wherein an effective geometry is employed for said multi-layer dielectric layers.

20. The method of claim 1, wherein one or more of said interconnects comprises a multi-conductor layer.

21. The method of claim 20, wherein said multi-conductor layer is a copper damascene layer.

22. The method of claim 20, wherein an effective geometry is employed for said multi-conductor layer.

23. A computer readable storage device embodying a program of instructions executable by a computer to perform a method of establishing a set of parameter values for use in simulating the operation of an integrated circuit, the integrated circuit being formed of a structure comprising a conductive layer formed upon a substrate and a plurality of interconnect layers formed over the conductive layer, and including inter-layer and intra-layer dielectrics and a dielectric layer over the topmost of the interconnect layers, said method comprising:

for a first portion of the structure, characterized by a first subset of the parameters and including a first of said layers and a second layer adjacent to the first layer, optimizing the first portion of the structure to establish values for the first subset of the parameters; and

for a second portion of the structure, characterized by a second subset of parameters and including the second of said layers and a third layer adjacent the second layer and distinct from the first, subsequently optimizing the second portion of the structure to establish values for the second subset, wherein the first and second subset share one or more of the parameters and the second subset is optimized holding the previously established values for the first subset fixed.

24. The method of claim 23, wherein said method is performed as a semi-automatic process.

25. The method of claim 23, wherein said method is performed as a manual process.

26. A method for transmitting a program of instructions executable by a computer to perform a process of establishing a set of parameter values for use in simulating the operation of an integrated circuit, the integrated circuit being formed of a structure comprising a conductive layer formed upon a substrate and a plurality of interconnect layers formed over the conductive layer, and including inter-layer and intra-layer dielectrics and a dielectric layer over the topmost of the interconnect layers, said process comprising:

for a first portion of the structure, characterized by a first subset of the parameters and including a first of said layers and a second layer adjacent to the first layer, optimizing the first portion of the structure to establish values for the first subset of the parameters; and

for a second portion of the structure, characterized by a second subset of parameters and including the second of said layers and a third layer adjacent the second layer and distinct from the first, subsequently optimizing the second portion of the structure to establish values for the second subset, wherein the first and second subset share one or more of the parameters and the second subset is optimized holding the previously established values for the first subset fixed.

27. The method of claim 26, wherein said process is performed as a semi-automatic process.

28. The method of claim 26, wherein said process is performed as a manual process.