Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction
First Claim
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1. A method for making a semiconductor device comprising:
- forming a dielectric layer on a substrate;
forming a trench within the dielectric layer, the trench having a sidewall;
exposing at least part of the sidewall to fluorine to inhibit formation of a high-k dielectric layer on the surface of the sidewall; and
forming a high-k gate dielectric layer within the trench without forming a meaningful amount of a high-k dielectric layer on the surface of the sidewall.
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Abstract
A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface.
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Citations
6 Claims
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1. A method for making a semiconductor device comprising:
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forming a dielectric layer on a substrate;
forming a trench within the dielectric layer, the trench having a sidewall;
exposing at least part of the sidewall to fluorine to inhibit formation of a high-k dielectric layer on the surface of the sidewall; and
forming a high-k gate dielectric layer within the trench without forming a meaningful amount of a high-k dielectric layer on the surface of the sidewall. - View Dependent Claims (2, 3)
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4. A method for making a semiconductor device comprising:
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forming a dielectric layer on a substrate;
forming a first trench within the dielectric layer, the first trench having a first sidewall;
modifying at least part of the first sidewall;
forming a first high-k gate dielectric layer within the first trench;
forming a first metal layer on the first high-k gate dielectric layer;
forming a second trench within the dielectric layer, the second trench having a second sidewall;
modifying at least part of the second sidewall;
forming a second high-k gate dielectric layer within the second trench; and
forming a second metal layer on the second high-k ate dielectric layer;
wherein the first metal layer and the second metal layer meet at a P/N junction. - View Dependent Claims (5, 6)
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Specification