Substrate mapping

• US 6,888,159 B2
• Filed: 10/25/2002
• Issued: 05/03/2005
• Est. Priority Date: 08/22/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Gochnour, Derek J.
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/280,415
• Publication Number:
  US 20030047805A1
• Time in Patent Office: 921 Days
• Field of Search: 257/48, 257/666, 257/676, 257/782, 257/797, 158/64, 297/10
• US Class Current: 257/48
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/53043 including means to divert defective work part
• CPC Class Codes: Y10T 29/53178 Chip component
• CPC Class Codes: Y10T 29/53187 Multiple station assembly apparatus

Abstract

A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.

Claims

1. A mounting substrate assembly comprising:

a substrate having a designator having encoded information, said encoded information comprising information uniquely identifying said substrate, on a peripheral portion of said substrate, a first surface and a second surface, at least one of said first surface and said second surface including a plurality of pretested die sites, each of said plurality of pretested die sites categorized as one of a defective die site and a good die site; and

at least one pretested defective die and at least one pretested good die configured to attach to said plurality of pretested die sites, said at least one pretested defective die attached to each of said defective die sites and said at least one pretested good die attached to each of said good die sites.

2. The assembly of claim 1, wherein each of said at least one pretested defective die and said at least one pretested good die attached to said substrate includes an encapsulation material formed thereon.

3. The assembly of claim 1, further comprising an encapsulation material encapsulating each of said at least one pretested defective die and each of said at least one pretested good die and at least partially encapsulating said substrate.

4. The assembly of claim 3, wherein said encapsulation material is prevented from forming over said designator.

5. The assembly of claim 1, wherein said designator includes identification information.

6. The assembly of claim 1, wherein said designator includes mapped information of said substrate.

7. The assembly of claim 1, wherein said designator is configured to access mapped information of said substrate.

8. The assembly of claim 1, wherein said encoded information of said designator comprises information configured as a bar code.

9. The assembly of claim 8, wherein said bar code is inscribed on said peripheral portion of said substrate by directed optical energy.

10. The assembly of claim 1, wherein said encoded information comprises information configured on a strip of magnetic tape.

11. The assembly of claim 1, wherein said encoded information further comprises information which chronicles a manufacturing process history for said substrate.

12. The assembly of claim 1, wherein said encoded information comprises instructions for orientation of a pin one of a semiconductor die relative to each of said at least one pretested defective die site and each of said at least one pretested good die site.

13. The assembly of claim 1, wherein said encoded information comprises at least one identifying mark selected from at least one of alphanumeric characters, symbols, colors, binary sequences, and combinations of any thereof.

14. The assembly of claim 1, wherein said encoded information comprises information relating to testing and inspection of said substrate.

15. The assembly of claim 1, wherein said substrate is a carrier substrate.

16. The assembly of claim 1, wherein said substrate is a lead frame array.

17. A substrate assembly comprising:

a substrate having a designator having encoded information, said encoded information comprising information uniquely identifying said substrate, on a peripheral portion of said substrate, a first surface and a second surface, at least one of said first surface and said second surface including a plurality of pretested die sites, each of said plurality of pretested die sites determined to be one of a defective die site and a good die site; and

at least one pretested defective die and at least one pretested good die for attaching to said plurality of pretested die sites, said at least one pretested defective die attached to each of said defective die sites and said at least one pretested good die attached to each of said good die sites.

18. The assembly of claim 17, wherein each of said at least one pretested defective die and said at least one pretested good die attached to said substrate includes an encapsulation material formed thereon.

19. The assembly of claim 17, further comprising an encapsulation material encapsulating each of said at least one pretested defective die and each of said at least one pretested good die and at least partially encapsulating said substrate.

20. The assembly of claim 19, wherein said encapsulation material is prevented from substantially forming over said designator.

21. The assembly of claim 17, wherein said designator includes identification information.

22. The assembly of claim 17, wherein said designator includes mapped information of said substrate.

23. The assembly of claim 17, wherein said designator is configured to access mapped information of said substrate.

24. The assembly of claim 17, wherein said encoded information of said designator comprises information configured as a bar code.

25. The assembly of claim 24, wherein said bar code is inscribed on said peripheral portion of said substrate by directed optical energy.

26. The assembly of claim 17, wherein said encoded information comprises information for storage on a strip of magnetic tape.

27. The assembly of claim 22, wherein said encoded information further comprises information for a manufacturing process history for said substrate.

28. The assembly of claim 17, wherein said encoded information comprises at least one instruction for orientation of a pin one of a semiconductor die relative to each of said at least one pretested defective die site and each of said at least one pretested good die site.

29. The assembly of claim 17, wherein said encoded information comprises at least one identifying mark selected from at least one of alphanumeric characters, symbols, colors, binary sequences, and combinations of any thereof.

30. The assembly of claim 17, wherein said encoded information comprises information relating to at least one of testing and inspection of said substrate.

31. The assembly of claim 17, wherein said substrate is a carrier substrate.

32. The assembly of claim 17, wherein said substrate is a lead frame array.