Nonvolatile semiconductor memory device, manufacturing method thereof, and operating method thereof

• US 6,888,194 B2
• Filed: 02/26/2003
• Issued: 05/03/2005
• Est. Priority Date: 02/27/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yoshino, Akira
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/374,840
• Publication Number:
  US 20030160280A1
• Time in Patent Office: 797 Days
• Field of Search: 257/324, 257/315, 257/316, 257/317
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Nonvolatile memory elements are disclosed which can have increased capacity, reduced operating voltage and/or faster operating speeds. According to one embodiment, a nonvolatile memory element can include a first diffusion layer (2) and a second diffusion layer (3) formed in a main surface of a substrate (1). A laminate film can be formed near a first diffusion layer (2) and/or a second diffusion layers (3) that includes a first insulating film (4a or 4), a second insulating film (5a or 5), and a third insulating film (6a or 6). A gate insulating film (7) can be formed a channel region and gate electrode (8) can be formed to cover gate insulating film (7) and the laminate film(s) that has a T-shape. A gate electrode (8) can have end portions that sandwich a first insulating film (4a or 4), a second insulating film (5a or 5), and a third insulating film (6a or 6) with a first diffusion layer (2) and/or second diffusion layer (3).

Claims

1. A nonvolatile memory device, comprising:

a first diffusion layer and second diffusion layer separated by a channel region;

a first insulating layer for trapping a charge formed on a first portion of the channel region adjacent to the first diffusion layer;

a second insulating layer, different than the first insulating layer, formed on a second portion of the channel region different from the first portion of the channel region; and

an integrated gate electrode that covers the first insulating layer and second insulating layer.

2. The nonvolatile memory device of claim 1, wherein:

a capacitance per unit area of the second insulating layer is larger than that of the first insulating layer.

3. The nonvolatile memory device of claim 1, wherein:

the first insulating layer is a laminate structure comprising a first silicon oxide film, a different film, and a second silicon oxide film, the different film being selected from the group of a silicon nitride film and a metal oxide film.

4. The nonvolatile memory device of claim 1, wherein:

the integrated gate electrode has a “

T”

shape in cross section taken along a channel length direction.

5. The nonvolatile memory device of claim 1, wherein:

the integrated gate electrode includes end portions, and the first insulating layer is sandwiched between at least one end portion and the first diffusion layer.

6. The nonvolatile memory device of claim 1, wherein:

the integrated gate electrode includes a central portion formed over the second insulating layer and at least one end portion formed over the first insulating layer, the at least one end portion being formed from a different material than the central portion.

7. The nonvolatile memory device of claim 1, further including:

a word line of a memory cell array coupled to the gate electrode; and

a bit line of a memory cell array formed from at least one of the diffusion layers.

8. The nonvolatile memory device of claim 7, wherein:

the word line is essentially orthogonal to the bit line.

9. The nonvolatile memory device of claim 1, further including:

a third insulating layer that covers the first diffusion layer having a larger capacitance per unit area than the first insulating layer; and

a conductive layer formed on the third insulating layer.