One transistor SOI non-volatile random access memory cell
First Claim
1. A semiconductor structure, comprising:
- a substrate;
a buried insulator layer positioned over at least a portion of the substrate;
a body region positioned over the buried insulator layer, the body region including a charge trapping region;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer.
8 Assignments
0 Petitions
Accused Products
Abstract
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.
-
Citations
83 Claims
-
1. A semiconductor structure, comprising:
-
a substrate;
a buried insulator layer positioned over at least a portion of the substrate;
a body region positioned over the buried insulator layer, the body region including a charge trapping region;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A semiconductor structure, comprising:
-
a substrate;
a buried insulator layer positioned over at least a portion of the substrate;
a body region positioned over the buried insulator layer;
a charge trapping region formed at an interface between the buried insulator layer and the body region;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A semiconductor structure, comprising:
-
a substrate;
a buried insulator layer positioned over at least a portion of the substrate;
a body region positioned over the buried insulator layer;
a charge trapping region formed in the body region near an interface between the buried insulator layer and the body region;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (15, 16, 17, 18)
-
-
19. A semiconductor structure, comprising:
-
a substrate;
a buried insulator layer positioned over at least a portion of the substrate;
a body region positioned over the buried insulator layer, the body region including a charge trapping oxynitride region, the oxynitride region having a refractive index within a range of approximately 1.75 to approximately 1.9;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (20, 21)
-
-
22. A semiconductor structure, comprising:
-
a substrate;
a buried insulator layer positioned over at least a portion of the substrate;
a body region positioned over the buried insulator layer, the body region including a charge trapping composite;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (23, 24, 25, 26)
-
-
27. A semiconductor structure, comprising:
-
a substrate;
a buried insulator layer positioned over at least a portion of the substrate;
a body region positioned over the buried insulator layer, the body region including a charge trapping laminate;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (28, 29, 30, 31)
-
-
32. A memory cell, comprising:
-
a substrate;
a buried insulator layer formed on the substrate; and
a transistor formed on the buried insulator layer, including;
a floating body region, including a charge trapping region within the floating body region, the charge trapping region including silicon nitride (Si3N4);
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (33, 34)
-
-
35. A memory cell, comprising:
-
a substrate;
a buried insulator layer formed on the substrate; and
a transistor formed on the buried insulator layer, including;
a floating body region, including a charge trapping region within the floating body region, the charge trapping region including an oxynitride;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (36, 37)
-
-
38. A memory cell, comprising:
-
a substrate;
a buried insulator layer formed on the substrate; and
a transistor formed on the buried insulator layer, including;
a floating body region, including a charge trapping region within the floating body region, the charge trapping region including a metal oxide;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (39, 40, 41)
-
-
42. A memory cell, comprising:
-
a substrate;
a buried insulator layer formed on the substrate; and
a transistor formed on the buried insulator layer, including;
a floating body region, including a charge trapping region within the floating body region, the charge trapping region including a metal silicide;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (43, 44)
-
-
45. A memory cell, comprising:
-
a substrate;
a buried insulator layer formed on the substrate; and
a transistor formed on the buried insulator layer, including;
a floating body region, including a charge trapping composite within the floating body region;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (46, 47, 48, 49)
-
-
50. A memory cell, comprising:
-
a substrate;
a buried insulator layer formed on the substrate; and
a transistor formed on the buried insulator layer, including;
a floating body region, including a charge trapping laminate within the floating body region;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (51, 52, 53, 54)
-
-
55. A memory cell, comprising:
-
a substrate;
a buried insulator layer formed on the substrate; and
a transistor formed on the buried insulator layer, including;
a floating body region having a number of sidewalls, the floating body region including a sidewall charge trapping region at or near at least a portion of at least one of the number of sidewalls;
a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
a gate insulator layer formed over the channel region; and
a gate formed over the gate insulator layer. - View Dependent Claims (56, 57, 58)
-
-
59. A method of forming a non-volatile memory cell, comprising:
-
forming a body region over a buried oxide (BOX) insulator on a substrate;
forming a charge trapping region in the body region;
forming a first diffusion region and a second diffusion region to define a channel region in the body region;
forming a gate dielectric over the channel region; and
forming a gate over the gate dielectric. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72)
-
-
73. A method of forming a non-volatile memory cell, comprising:
-
forming a body region over a buried oxide (BOX) insulator on a substrate;
forming a charge trapping silicon nitride (Si3N4) region in the body region;
forming a first diffusion region and a second diffusion region to define a channel region in the body region;
forming a gate dielectric over the channel region; and
forming a gate over the gate dielectric. - View Dependent Claims (74, 75)
-
-
76. A method of forming a non-volatile memory cell, comprising:
-
forming a body region over a buried oxide (BOX) insulator on a substrate;
forming a charge trapping oxynitride region in the body region;
forming a first diffusion region and a second diffusion region to define a channel region in the body region;
forming a gate dielectric over the channel region; and
forming a gate over the gate dielectric. - View Dependent Claims (77, 78, 79, 80, 81, 82, 83)
-
Specification