High performance, low cost microelectronic circuit package with interposer

• US 6,888,240 B2
• Filed: 04/30/2001
• Issued: 05/03/2005
• Est. Priority Date: 04/30/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vandentop, Gilroy, Towle, Steven, Tang, John
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US09/845,896
• Publication Number:
  US 20020158335A1
• Time in Patent Office: 1,464 Days
• Field of Search: 257/723, 257/724, 257/924, 257/778, 257/787, 257/691, 257/698, 257/697, 257/777, 257/702, 257/738, 257/780, 257/773
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10S 257/924 with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

A low cost technique for packaging microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuit using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core assembly before lamination of the interposer.

Claims

1. A microelectronic device comprising:

a die having an active surface fixed within an opening in a package core by an encapsulation material between said die and said package core;

a metallization layer built up upon said active surface of said die and said package core; and

a grid array interposer unit having a first surface laminated to said metallization layer, said grid array interposer unit having an array of electrical contacts on a second surface thereof for connection to an external circuit board, wherein said grid array interposer unit includes an opening that exposes a first portion of said metallization layer, said microelectronic device further comprising at least one de-coupling capacitor connected to said first portion of said metallization layer to provide de-coupling for circuitry within said die.

2. The microelectronic device of claim 1, wherein:

said package core is formed from a dielectric board material having metallic cladding on at least one surface thereof.

3. The microelectronic device of claim 2, wherein:

said metallic cladding is conductively coupled to ground during operation of said device to provide a ground plane for at least one transmission structure within said metallization layer.

4. The microelectronic device of claim 2, wherein:

said metallic cladding is conductively coupled to a power source during device operation to form a power plane.

5. The microelectronic device of claim 2, wherein:

said metallization layer includes at least one ground pad that is conductively coupled to said metallic cladding on said package core through one or more via connections.

6. The microelectronic device of claim 1, wherein:

said active surface includes a plurality of power bars and a plurality of ground bars, each of said plurality of power bars being conductively coupled to multiple power bond pads of said die and each of said plurality of ground bars being conductively coupled to multiple ground bond pads of said die.

7. The microelectronic device of claim 6, wherein:

said plurality of power bars and said plurality of ground bars are interleaved within a central region of said active surface of said die.

8. The microelectronic device of claim 6, wherein:

said die includes a plurality of signal contact pads distributed within a peripheral region of said active surface.

9. The microelectronic device of claim 1, wherein:

said metallization layer includes at least one power landing pad situated over said die, said at least one power landing pad being conductively coupled to multiple power bond pads on said die through corresponding via connections.

10. The microelectronic device of claim 9, wherein:

said metallization layer includes at least one ground landing pad situated over said die, said at least one ground landing pad being conductively coupled to multiple ground bond pads on said die through corresponding via connections.

11. The microelectronic device of claim 1, wherein:

said metallization layer includes at least one power landing pad situated over said package core, said at least one power landing pad being conductively coupled to multiple power bond pads on said die through a trace portion extending over said die and a plurality of via connections.

12. The microelectronic device of claim 1, wherein:

said metallization layer includes at least one signal landing pad situated over said package core, said at least one signal landing pad being conductively coupled to a signal bond pad on said die through a path including a transmission line segment.

13. The microelectronic device of claim 1, wherein:

said microelectronic device includes a single metallization layer between said die and said grid array interposer unit.

14. An electrical system comprising:

a microelectronic device having;

a die/core assembly including a die fixed within an opening in package core by an encapsulation material between said die and said package core, said die/core assembly having a first surface including an active surface of said die;

a metallization layer built up over said first surface of said die/core assembly, said metallization layer having a first metallization portion over said die and a second metallization portion over said package core;

a grid array interposer unit laminated to said metallization layer, said grid array interposer unit having a first array of electrical contacts on a surface thereof; and

at least one capacitor conductively coupled to an exposed portion of said metallization layer to provide de-coupling for circuitry within said microelectronic die; and

a circuit board having a second array of electrical contacts, said grid array interposer unit being coupled to said circuit board so that contacts within said first array of electrical contacts are conductively coupled to corresponding contacts within said second array of electrical contacts.

15. The electrical system claimed in claim 14, wherein:

said circuit board is a computer motherboard.

16. The electrical system of claim 15, wherein:

said first array of electrical contacts includes a plurality of pins.

17. The electrical system of claim 15, wherein:

said first array of electrical contacts includes a plurality of solder balls.

18. A microelectronic device comprising:

a die/core assembly having a microelectronic die fixed within an opening in a package core by an encapsulation material between said die and said package core, said die/core assembly having including a first surface including an active surface of said die;

a metallization layer built up over said first surface of said die/core assembly, said metallization layer having a first metallization portion over said die and a second metallization portion over said package core;

a grid array interposer unit laminated to said metallization layer; and

at least one capacitor conductively coupled to an exposed portion of said metallization layer to provide de-coupling for circuitry within said microelectronic die.

19. The microelectronic device of claim 18, wherein:

said metallization layer includes at least one power landing pad situated over said microelectronic die that is conductively coupled to multiple power bond pads on said die and also to a corresponding power contact on said grid array interposer unit.

20. The microelectronic device of claim 18, wherein:

said metallization layer includes at least one power landing pad situated over said package core that is conductively coupled to multiple power bond pads on said die and also to a corresponding power contact on said grid array interposer unit.

21. A microelectronic device comprising:

a die having an active surface fixed within opening in a package core by an encapsulation material between said die and said package core;

a metallization layer built up upon said active surface of said die and said package core, wherein said metallization layer includes a first metallization portion located over said die and a second metallization portion located over said package core; and

a grid array interposer unit having a first surface laminated to said metallization layer, said grid array interposer unit having an array of electrical contacts on a second surface thereof for connection to an external circuit board, and wherein said grid array interposer unit has a thickness between said first and second surfaces that is no greater than 0.5 millimeters and said grid array interposer unit includes an opening that exposes a first portion of said metallization layer, said microelectronic device further comprising at least one de-coupling capacitor connected to said first portion of said metallization layer to provide de-coupling for circuitry within said die.

22. The microelectronic device of claim 21, wherein:

said metallization layer includes at least one ground pad that is conductively coupled to said metallic cladding on said package core through one or more via connections.

23. A microelectronic device comprising:

a die having an active surface fixed within a package core;

a metallization layer adjacent to said active surface of said die and said package core;

a grid-array interposer unit having a first surface laminated to said metallization layer, said grid array interposer unit having an array of electrical contacts on a second surface thereof for connection to an external circuit board; and

a dielectric layer between said metallization layer and said active surface of said die and said package core.

24. The microelectronic device of claim 23, wherein:

said metallization layer is conductively coupled to said active surface of said die through via connections in said dielectric layer.

25. The microelectronic device of claim 23, wherein:

said metallization layer includes ate least one I/O landing pad to said active surface of said die by a transmission line segment.

26. A microelectronic device comprising:

a die/core assembly including a die fixed within a package core, said die/core assembly having a continuous surface;

a metallization layer built up upon said continuous surface; and

a grid array interposer unit having a first surface laminated to said metallization layer, said grid array interposer unit having an array of electrical contacts on a second surface thereof for connection to an external circuit board.

27. The microelectronic device of claim 26, wherein:

said die is fixed within said package care by an encapsulation material between said die and said package core.

28. The microelectronic device of claim 27, wherein:

said package core includes an opening that extends through said package core.

29. The microelectronic device of claim 26, wherein:

said continuous surface comprises a dielectric layer.

30. The microelectronic device of claim 28, wherein:

said metallization layer is conductively coupled to said active surface of said die through via connections in said dielectric layer.

31. The microelectronic device of claim 26, wherein:

said package core comprises a metallic cladding on at least one surface thereof.

32. The microelectronic device of claim 31, wherein:

said metallic cladding is conductively coupled to ground during device operation to provide a ground plane.

33. The microelectronic device of claim 31, wherein:

said metallic cladding is conductively coupled to a power source during device operation to provide a power plane.

34. The microelectronic device of claim 26, wherein:

said metallization layer includes a power landing pad situated over said die, said power landing pad being conductively coupled to a power bond pad on said die through a via connection.

35. The microelectronic device of claim 26, wherein:

said metallization layer includes a ground landing pad situated over said die, said ground landing pad being conductively coupled to a ground bond pad on said die through a via connection.

36. The microelectronic device of claim 26, wherein:

said metallization layer includes a signal landing pad situated over said package core, said signal landing pad being conductively coupled to a signal bond pad on said die through a transmission line segment.

37. The microelectronic device of claim 26, further comprising:

a de-coupling capacitor connected to said second surface of said grid array interposer unit to provide de-coupling for circuitry within said die.

38. The microelectronic device of claim 26, further comprising:

a circuit board having a second array of electrical contacts, wherein said grid array interposer unit is conductively coupled to said circuit board.