Tileable field-programmable gate array architecture

• US 6,888,375 B2
• Filed: 04/30/2003
• Issued: 05/03/2005
• Est. Priority Date: 09/02/2000
• Status: Expired due to Term

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Xiong, Weidong, Liao, Naihui, Liu, Tong, Sun, Chung-yuan, Huang, Eddy C., Lien, Jung-Cheun, Feng, Sheng
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/429,002
• Publication Number:
  US 20030218479A1
• Time in Patent Office: 734 Days
• Field of Search: 326 38- 41
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3947 global
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

Claims

1. A system of routing resources in a field-programmable gate array (FPGA) comprising:

a first FPGA tile comprising;

a plurality of functional groups (FGs) arranged in rows and columns, each configureable to perform Boolean functions, each FG having a first, second and third set of input ports and a first and second set of output ports;

a first set of routing conductors disposed within said first FPGA tile programmably coupled to said first set of output ports of said logic components and configured to receive signals, route signals within said first FPGA tile, and provide said signals to said first set of input ports of said logic components;

a second set of routing conductors disposed across said first FPGA tile and at least one other FPGA tile, independent of said first set of routing conductors coupled to said second set of output ports and that is configured to receive, select and route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said second set of input ports of said logic components; and

a third set of routing conductors disposed across said first FPGA tile, independent of said first and second set of routing conductors, coupled to at least one of said first output ports of said logic components, and employing a plurality of tracks and a plurality of switches to receive signals, route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said third set of input ports of said logic components when said first set of routing conductors cannot be used.

2. The system of claim 1 wherein said plurality of tracks intersect at a plurality of routing interconnect areas.

3. The system of claim 2 wherein at least one of said plurality of routing interconnect areas is fully populated with said plurality of switches.

4. The system of claim 2 wherein at least one of said plurality of routing interconnect areas is not fully populated with said plurality of switches.

5. A system of routing resources in a field-programmable gate array (EPGA) comprising:

a first FPGA tile comprising;

a plurality of functional groups (FGs) arranged in rows and columns, each of the FGs having a first, second and third set of input ports and first and second set of output ports, and configured to receive input signals through designated ports, perform logic operations and generate output signals;

a third set of routing conductors independent of a first and a second set of routing conductors, coupled to said first set of output ports of said FGs, and employing a plurality of tracks and a plurality of switches to receive said output signals, select and route said signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said first set of input ports when said first set of routing conductors cannot be used; and

a plurality of interface groups (IGs) surrounding the plurality of FGs such that one IG is positioned at each end of each row and column, each of the IGs having a first, second and third set of input ports and first and second set of output ports and coupled to said third set of routing conductors and configured to transfer signals from said third set of routing conductors to outside of said first FPGA tile.

6. The system of claim 5, wherein said plurality of tracks intersect at a plurality of routing interconnect areas.

7. The system of claim 6, wherein at least one of said plurality of routing interconnect areas is fully populated with said plurality of switches.

8. The system of claim 6 wherein at least one of said plurality of routing interconnect areas is not fully populated with said plurality of switches.

9. The system of claim 5, wherein said FPGA further comprises:

a second FPGA tile that includes a plurality of FGs, a third set of routing conductors, and a plurality of IGs arranged in the same manner as the first FPGA tile, wherein at least one IG of said first FPGA tile is coupled to at least one IG of said second FPGA tile by said third set of routing conductors.

10. The system of claim 5, wherein said FPGA further comprises:

a second FPGA tile that includes a plurality of FGs, a third set of routing conductors, and a plurality of IGs arranged in a manner substantially similar to said first FPGA tile, wherein at least one IG of said first FPGA tile is coupled to at least one IG of said second FPGA tile.

11. A method of providing a system of routing resources in a field-programmable gate array (FPGA) comprising:

providing a first FPGA tile comprising;

providing a plurality of functional groups (FGs) arranged in rows and columns, each configureable to perform Boolean functions, each FG having a first, second and third set of input ports and a first and second set of output ports;

providing a first set of routing conductors disposed within said first FPGA tile programmably coupled to said first set of output ports of said logic components and configured to receive signals, route signals within said first FPGA tile, and provide said signals to said first set of input ports of said logic components;

providing a second set of routing conductors disposed across said first FPGA tile and at least one other FPGA tile, independent of said first set of routing conductors coupled to said second set of output ports and that is configured to receive, select and route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said second set of input ports of said logic components; and

providing a third set of routing conductors disposed across said first FPGA tile, independent of said first and second set of routing conductors, coupled to at least one of said first output ports of said logic components, and employing a plurality of tracks and a plurality of switches to receive signals, route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said third set of input ports of said logic components when said first set of routing conductors cannot be used.

12. The method of claim 11 wherein said plurality of tracks intersect at a plurality of routing interconnect areas.

13. The method of claim 12 wherein at least one of said plurality of routing interconnect areas is fully populated with said plurality of switches.

14. The method of claim 12 wherein at least one of said plurality of routing interconnect areas is not fully populated with said plurality of switches.