Multi-cascode transistors

• US 6,888,396 B2
• Filed: 03/11/2003
• Issued: 05/03/2005
• Est. Priority Date: 03/11/2002
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Hajimiri, Seyed-Ali, Kee, Scott D., Aoki, Ichiri
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US10/385,769
• Publication Number:
  US 20040027755A1
• Time in Patent Office: 784 Days
• Field of Search: 327/427, 327/436, 327/581
• US Class Current: 327/427
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/226 with junction-FET's
• CPC Class Codes: H03F 2203/45301 there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 3/42 Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
• CPC Class Codes: H03F 3/423 with MOSFET's
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence

Abstract

A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

Claims

1. A cascode power circuit for providing improved withstand voltage for radio frequency switching transistors comprising:

three or more transistors, each having a control terminal and two conduction terminals, wherein the conduction terminals are coupled in series between two output terminals;

a radio frequency signal input coupled to the control terminal for the first transistor; and

two or more control voltage sources, each coupled to a corresponding control terminal for the remaining transistors, the control voltage sources maintaining the voltage across each corresponding transistor to a level below a breakdown voltage level;

wherein a voltage drop across the three or more transistors exceeds a withstand voltage of any one of the three or more transistors, and wherein the control voltage sources are magnetically coupled to the signal input.

2. The cascode circuit of claim 1 wherein the control voltage sources are linear circuits.

3. The cascode circuit of claim 1 wherein the control voltage sources are non-linear circuits.

4. The cascode circuit of claim 1 wherein each control voltage source is coupled to one or more of the conduction terminals for the associated transistor.

5. The cascode circuit of claim 1 wherein the control voltage sources are capacitively coupled to one or more of the conduction terminals for the associated transistor.

6. The cascode circuit of claim 1 wherein the control voltage sources are resistively coupled to one or more of the conduction terminals for the associated transistor.

7. The cascode circuit of claim 1 wherein the control voltage sources are coupled to one or more of the conduction terminals for the associated transistor by diode drivers.

8. The cascode circuit of claim 1 further comprising a second cascode circuit having the same number of transistors, wherein the first cascode circuit and the second cascode circuit are coupled to form a differential cascade circuit.

9. A cascode circuit for providing improved withstand voltage for radio frequency switching transistors comprising:

two or more transistors, each having a control terminal and two conduction terminals, wherein the conduction terminals are coupled in series between two output terminals;

a radio-frequency signal input coupled to the control terminal for the first transistor, and one or more control voltage circuits, each coupled to a corresponding control terminal and to one or more of the conduction terminals for the remaining transistors, the control voltage circuits maintaining the voltage across each corresponding transistor to a level below a breakdown voltage level;

wherein a peak voltage across the three or more transistors exceeds a withstand voltage of anyone of the three or more transistors, and wherein the control voltage sources are magnetically coupled to the signal input.

10. The cascode circuit of claim 9 wherein the control voltage circuits are circuits.

11. The cascode circuit of claim 9 wherein the control voltage sources are non-linear circuits.

12. The cascode circuit of claim 9 wherein the control voltage sources are capacitively coupled to one or more of the conduction terminals for the associated transistor.

13. The cascode circuit of claim 9 wherein the control voltage sources are resistively coupled to one or more of the conduction terminals for the associated transistor.

14. The cascode circuit of claim 9 wherein the control voltage sources are coupled to one or more of the conduction terminals for the associated transistor by diode drivers.

15. The cascode circuit of claim 9 further comprising a second cascode circuit having the same number of transistors, wherein the first cascode circuit and the second cascode circuit are coupled to form a differential cascode circuit.

16. A method for providing increased withstand voltage capability for radio frequency switching transistors comprising:

connecting three or more transistors in series between two output terminals;

providing a radio frequency input signal to control input of one of the transistors;

providing a control voltage to the control input of each of the remaining transistors so as to maintain the voltage across each of the transistors to a level below a breakdown voltage;

wherein a peak voltage across the three or more transistors exceeds an operating voltage of any one of the three or more transistors; and

wherein the control voltage sources are magnetically coupled to the radio frequency input signal.

17. The method of claim 16 wherein providing the control voltage to the control input of each of the remaining transistors comprises providing a DC bias voltage.

18. The method of claim 16 wherein providing the control voltage to the control input of each of the remaining transistors comprises deriving a voltage from a conduction terminal of each corresponding transistor.