Array substrate for liquid crystal display and method for fabricating the same

• US 6,888,586 B2
• Filed: 11/28/2001
• Issued: 05/03/2005
• Est. Priority Date: 06/05/2001
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Jo, Gyoo Chul, Yoo, Hong Suk
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Sefer, Ahmed N.
• Application Number:
  US09/994,809
• Publication Number:
  US 20020180898A1
• Time in Patent Office: 1,252 Days
• Field of Search: 349/43, 349/42, 349/147, 257/59, 257/72
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

An array substrate for a liquid crystal display device includes a substrate; a drain electrode at an upper portion of the substrate, the drain electrode including, at least in part, two layers of conductive materials and having a first drain contact hole penetrating the two layers; a protective layer over the drain electrode, the protecting layer having a second drain contact hole communicating with the first drain contact hole; and a pixel electrode over the protective layer, the pixel electrode contacting the drain electrode at inner surfaces of the first drain contact hole formed in the drain electrode through the second drain contact hole.

Claims

1. An array substrate for a liquid crystal display device, comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating film covering the gate electrode;

an active layer overlapping the gate electrode over the gate insulating film;

an ohmic contact layer on a part of the active layer, the ohmic contact layer defining a channel region in the active layer;

a drain electrode at an upper portion of the substrate, the drain electrode including, at least in part, two layers of conductive materials and having a first drain contact hole penetrating the two layers such that sides of the two layers are exposed at all inner side surfaces of the first drain contact hole;

a protective layer over the drain electrode, the protecting layer having a second drain contact hole communicating with the first drain contact hole; and

a pixel electrode over the protective layer, the pixel electrode contacting the drain electrode at the inner surfaces of the first drain contact hole formed in the drain electrode through the second drain contact hole,

wherein the gate insulating film is exposed through the first and second drain contact holes, and

wherein the pixel electrode directly contacts the exposed gate insulating film through the first and second drain contact holes.

2. The array substrate according to claim 1, wherein a width of the second drain contact hole is larger than or substantially equal to that of the first drain contact hole.

3. The array substrate according to claim 1, wherein said two layers of conductive materials includes a first metal layer and a second metal layer on the first metal layer, the first metal layer being one of molybdenum (Mo), chrome (Cr), tantalum (Ta), tungsten (W), and titanium (Ti), and the second metal layer being aluminum (Al) or an aluminum alloy.

4. The array substrate according to claim 1, further comprising:

a gate line, connected to the gate electrode, over the substrate for receiving a scanning signal;

a data line crossing the data line for receiving a data signal; and

a source electrode connected to the data line, the source electrode and said drain electrode being absent over the channel region and being in contact with the ohmic contact layer.

5. The array substrate according to claim 4, wherein said two layers includes a first metal layer and a second metal layer on the first metal layer, and

wherein the first metal layer and the second metal layer have substantially the same pattern.

6. The array substrate according to claim 4, further comprising:

a data pad at one end of the data line over the substrate, the data pad including, at least in part, said two layers of conductive materials, the data pad having a first data contact hole penetrating the two layers such that sides of the two layers are exposed at all inner side surfaces of the first data contact hole; and

a data pad terminal electrode over the protective layer,

wherein the protective layer is situated over the data pad, and has a second data contact hole communicating with the first data contact hole, and

wherein the data pad terminal electrode contacts the data pad at the inner surfaces of the first data contact hole formed in the data pad through the second data contact hole.

7. The array substrate according to claim 6, wherein a width of the second data contact hole is larger than or substantially equal to that of the first data contact hole.

8. The array substrate according to claim 6, wherein said two layers of conductive materials of the data pad include a first metal layer and a second metal layer on the first metal layer, the first metal layer being one of molybdenum (Mo), chrome (Cr), tantalum (Ta), tungsten (W), and titanium (Ti), and the second metal layer being aluminum (Al) or an aluminum alloy.

9. The array substrate according to claim 6, wherein the data pad is over the gate insulating film.

10. The array substrate according to claim 9, wherein said two layers of the data pad includes a first metal layer and a second metal layer on the first metal layer, and

wherein the data pad further includes a semiconductor layer beneath the first metal layer.

11. The array substrate according to claim 10, wherein the first metal layer of the two layers of the data pad and the underlying semiconductor layer have substantially the same pattern.

12. The array substrate according to claim 1, wherein the pixel electrode further electrically contacts at least one exposed side of the drain electrode through the first and second drain contact holes.

13. An array substrate for a liquid crystal display device, comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating film covering the gate electrode;

an active layer overlapping the gate electrode over the gate insulating film;

an ohmic contact layer on a part of the active layer, the ohmic contact layer defining a channel region in the active layer;

a drain electrode at an upper portion of the substrate, the drain electrode including, at least in part, two layers of conductive materials and having a first drain contact hole penetrating the two layers and the ohmic contact layer;

a protective layer over the drain electrode, the protecting layer having a second drain contact hole communicating with the first drain contact hole; and

a pixel electrode over the protective layer, the pixel electrode contacting the drain electrode at inner surfaces of the first drain contact hole formed in the drain electrode through the second drain contact hole,

wherein the active layer is exposed through the first and second drain contact holes, and

wherein the pixel electrode directly contacts the exposed active layer through the first and second drain contact holes.

14. The array substrate according to claim 13, wherein a width of the second drain contact hole is larger than or substantially equal to that of the first drain contact hole.

15. The array substrate according to claim 13, wherein said two layers of conductive materials include a first metal layer and a second metal layer on the first metal layer, the first metal layer being one of molybdenum (Mo), chrome (Cr), tantalum (Ta), tungsten (W), and titanium (Ti), and the second metal layer being aluminum (Al) or an aluminum alloy.

16. The array substrate according to claim 13, further comprising:

a gate line, connected to the gate electrode, over the substrate for receiving a scanning signal;

a data line crossing the data line for receiving a data signal; and

a source electrode connected to the data line, the source electrode and said drain electrode being absent over the channel region and being in contact with the ohmic contact layer.

17. The array substrate according to claim 16, wherein said two layers include a first metal layer and a second metal layer on the first metal layer, and

wherein the first metal layer and the ohmic contact layer thereunder have substantially the same pattern.

18. The array substrate according to claim 16, further comprising:

a data pad at one end of the data line over the substrate, the data pad including, at least in part, said two layers of conductive materials, the data pad having a first data contact hole penetrating the two layers; and

a data pad terminal electrode over the protective layer,

wherein the protective layer is situated over the data pad, and has a second data contact hole communicating with the first data contact hole, and

wherein the data pad terminal electrode contacts the data pad at inner surfaces of the first data contact hole formed in the data pad through a second data contact hole.

19. The array substrate according to claim 18, wherein a width of the second data contact hole is larger than or substantially equal to that of the first data contact hole.

20. The array substrate according to claim 18, wherein said two layers of conductive materials of the data pad includes a first metal layer and a second metal layer on the first metal layer, the first metal layer being one of molybdenum (Mo), chrome (Cr), tantalum (Ta), Tungsten (W), and titanium (Ti), and the second metal layer being aluminum (Al) or an aluminum alloy.

21. The array substrate according to claim 18, wherein the data pad is over the gate insulating film.

22. The array substrate according to claim 21, wherein said two layers of the data pad include a first metal layer and a second metal layer on the first metal layer, and

wherein the data pad further includes a semiconductor layer beneath the first metal layer.

23. The array substrate according to claim 22, wherein the first metal layer of the two layers of the data pad and the underlying semiconductor layer have substantially the same pattern.