Ferroelectric transistor for storing two data bits

• US 6,888,736 B2
• Filed: 11/26/2002
• Issued: 05/03/2005
• Est. Priority Date: 09/19/2002
• Status: Expired due to Fees

• Current Assignee: COVA Technologies Incorporated
• Original Assignee: COVA Technologies Incorporated
• Inventors: Dimmler, Klaus, Gnadinger, Alfred P.
• Primary Examiner(s): Nguyen, Van Thu
• Assistant Examiner(s): Luu, Pho M.
• Application Number:
  US10/305,205
• Publication Number:
  US 20040057319A1
• Time in Patent Office: 889 Days
• Field of Search: 365/145, 365/171
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A method of storing and accessing two data bits in a single ferroelectric FET includes selectively polarizing two distinct ferroelectric regions in the same gate dielectric layer separated by a non-ferroelectric dielectric region. A first ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the source and is polarized in one of two states to form a first data bit within the FET. A second ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the drain and is polarized in one of two states to form a second data bit within the FET. Detection of the first data bit is accomplished by selectively applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages.

Claims

1. A non-volatile memory storage method comprising:

providing an array of field effect transistors (FETs), wherein each FET in the array has a gate, drain, source, and substrate terminals, a first ferroelectric region between the gate and the source, and a second ferroelectric region between the gate and the drain, wherein the array is arranged in rows and columns, the gates of the FETs in a same row being coupled to a word line, the sources of FETs in a same column being coupled to a source bit line, and the drains of FETs in a same column being coupled to a drain bit line;

applying a voltage greater than the coercive voltage across a selected word line and a source bit line and the selected word line and the drain bit line of the same FET to polarize first and second ferroelectric regions associated with that FET to a first state while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a voltage greater than the coercive voltage across the selected word line and the source bit line in the opposite direction to polarize said first ferroelectric region of the selected FET to a second state while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a voltage less than the coercive voltage across the selected word line and the source bit line in the opposite direction to not polarize said first ferroelectric region of the selected FET while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a voltage greater than the coercive voltage across the selected word line and the drain bit line in the opposite direction to polarize said first ferroelectric region of the selected FET to a second state while leaving the polarization of all other ferroelectric materials in the array unchanged; and

applying a voltage less than the coercive voltage across the selected word line and the drain bit line in the opposite direction to not polarize said first ferroelectric region of the selected FET while leaving the polarization of all other ferroelectric materials in the array unchanged.

2. A non-volatile memory comprising a field effect transistor having a gate, drain, source, a first ferroelectric gate region, a second ferroelectric gate region and at least one buffer dielectric layer between the ferroelectric gate regions and a channel and/or between the ferroelectric gate regions and the gate, wherein the first and second ferroelectric gate regions are selectively polarized to first and second states without drawing a current between the source and the drain.

3. The memory of claim 2 wherein the buffer dielectric layer comprises a material selected from the group consisting of silicon nitride, silicon dioxide, and thermally grown silicon dioxide.

4. The memory of claim 2 wherein the buffer dielectric layer comprises two or more dielectric sub-layers.

5. The memory of claim 2 wherein the buffer dielectric layer is formed utilizing MOCVD or ALD.

6. The memory of claim 2 wherein the buffer dielectric layer comprises a material having a dielectric constant of 10 and greater.

7. The memory of claim 2 wherein the gate comprises a conductive electrode layer.

8. The memory of claim 7 wherein the conductive electrode layer comprises a polysilicon-containing material.

9. The memory of claim 2 wherein the ferroelectric gate regions comprise a material having the general formula A_xMn_yO_z where x, y, and z vary from 0.1 to 10 and A is a rare earth material selected from a group consisting of Ce, Pr, Nd, Pm, Sm, Eu, GD, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y and Sc.

10. The memory of claim 2 wherein the ferroelectric gate regions comprise a low-dielectric ferroelectric material.

11. The memory of claim 2 wherein the ferroelectric gate regions are formed using MOCVD.

12. The memory of claim 2 wherein the ferroelectric gate regions are formed using ALD.

13. The memory of claim 2 further comprising a silicon transistor substrate.

14. The memory of claim 2 further comprising a CMOS compatible transistor substrate.

15. The memory of claim 2 further comprising a silicon-on-insulator transistor substrate.

16. The memory of claim 2 further comprising an array of the field effect transistors.

17. A non-volatile memory comprising a field effect transistor having a gate, drain, source, a first ferroelectric gate region, and a second ferroelectric gate region wherein the first and second ferroelectric gate regions are selectively polarized to first and second states without drawing a current between the source and the drain,

wherein the ferroelectric gate regions comprise a material having the general formula A_xMn_yO_z where x, y, and z vary from 0.1 to 10 and A is a rare earth material selected from a group consisting of Ce, Pr, Nd, Pm, Sm, Eu, GD, Tb, Dv, Ho, Er, Tm, Yb, Lu, Y and Sc.

18. The memory of claim 17 further comprising at least one buffer dielectric layer between the ferroelectric gate regions and a channel and/or between the ferroelectric gate regions and the gate.

19. The memory of claim 18 wherein the buffer dielectric layer comprises a material selected from the group consisting of silicon nitride, silicon dioxide, and thermally grown silicon dioxide.

20. The memory of claim 18 wherein the buffer dielectric layer comprises two or more dielectric sub-layers.

21. The memory of claim 18 wherein the buffer dielectric layer is formed utilizing MOCVD or ALD.

22. The memory of claim 18 wherein the buffer dielectric layer comprises a material having a dielectric constant of 10 and greater.

23. The memory of claim 17 wherein the gate comprises a conductive electrode layer.

24. The memory of claim 23 wherein the conductive electrode layer comprises a polysilicon-containing material.

25. The memory of claim 17 wherein the ferroelectric gate regions comprise a low-dielectric ferroelectric material.

26. The memory of claim 17 wherein the ferroelectric gate regions are formed using MOCVD.

27. The memory of claim 17 wherein the ferroelectric gate regions are formed using ALD.

28. The memory of claim 17 further comprising a silicon transistor substrate.

29. The memory of claim 17 further comprising a CMOS compatible transistor substrate.

30. The memory of claim 17 further comprising a silicon-on-insulator transistor substrate.

31. The memory of claim 17 further comprising an array of the field effect transistors.

32. A non-volatile memory comprising a field effect transistor having a gate, drain, source, a first ferroelectric gate region, and a second ferroelectric gate region wherein the first and second ferroelectric gate regions are selectively polarized to first and second states without drawing a current between the source and the drain, wherein the ferroelectric gate regions are formed using MOCVD.

33. The memory of claim 32 wherein the ferroelectric gate regions comprise a material having the general formula A_xMn_yO_z where x, y, and z vary from 0.1 to 10 and A is a rare earth material selected from a group consisting of Ce, Pr, Nd, Pm, Sm, Eu, GD, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y and Sc.

34. The memory claim 32 further comprising at least one buffer dielectric layer between the ferroelectric gate regions and a channel and/or between the ferroelectric gate regions and the gate.

35. The memory of claim 32 further comprising an array of the field effect transistors.

36. A non-volatile memory comprising a field effect transistor having a gate, drain, source, a first ferroelectric gate region, and a second ferroelectric gate region wherein the first and second ferroelectric gate regions are selectively polarized to first and second states without drawing a current between the source and the drain, wherein the ferroelectric gate regions are formed using ALD.

37. The memory of claim 36 wherein the ferroelectric gate regions comprise a material having the general formula A_xMn_yO_z where x, y, and z vary from 0.1 to 10 and A is a rare earth material selected from a group consisting of Ce, Pr, Nd, Pm, Sm, Eu, GD, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y and Sc.

38. The memory of claim 36 further comprising at least one buffer dielectric layer between the ferroelectric gate regions and a channel and/or between the ferroelectric gate regions and the gate.

39. The memory of claim 36 further comprising an array of the field effect transistors.