Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

• US 6,888,750 B2
• Filed: 08/13/2001
• Issued: 05/03/2005
• Est. Priority Date: 04/28/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Petti, Christopher J., Johnson, Mark G., Walker, Andrew J., Kouznetsov, Igor G., Knall, N. Johan
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US09/927,642
• Publication Number:
  US 20010055838A1
• Time in Patent Office: 1,359 Days
• Field of Search: 365/185.01, 365/185.05, 365/185.06, 365/185.11, 365/185.12, 365/185.13, 365/185.14, 365/185.23, 365/185.26, 365/51, 365/72, 365/105, 365/175, 365/63, 365/94, 365/96, 365/97, 365/100, 365/103, 365/104, 365/129, 365/130, 365/173, 365/174, 365/176, 365/180, 257/204, 257/208, 257/209, 257/211
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.

Claims

1. A nonvolatile memory array, comprising:

an array of nonvolatile memory devices;

at least one driver circuit; and

a substrate;

wherein the at least one driver circuit is not located in a bulk monocrystalline silicon substrate, wherein the array of nonvolatile memory devices comprises an array of PROMs, EPROMS or EEPROMs, wherein the array of nonvolatile memory devices comprises a monolithic three dimensional array of memory devices.

2. The array of claim 1, wherein the array of nonvolatile memory devices comprises a three dimensional array of antifuses.

3. The array of claim 2, wherein the array of antifuses comprise a first set of rail stack conductors, a second set of rail stack conductors extending in a different direction than the first set of rail stack conductors, and an insulating layer disposed between the first and the second sets of rail stacks.

4. The array of claim 3, further comprising semiconductor diodes located at intersections of the conductors of the first and the second sets of rail stacks.

5. The array of claim 4, wherein the diodes comprise P+/N−

diodes.

6. The array of claim 1, wherein each device of the three dimensional array comprises:

a first conductor;

a second conductor; and

a pillar vertically disposed between the first and the second conductors;

wherein the pillar comprises;

a semiconductor diode having a first conductivity type region and a second conductivity type region;

a tunneling oxide;

a charge storage region; and

a blocking oxide.

7. The array of claim 6, wherein each charge storage region comprises:

an ONO dielectric film;

an insulating layer containing conductive nanocrystals;

or

an isolated floating gate comprising;

a tunnel dielectric above the channel;

the floating gate above the tunnel dielectric; and

a control gate dielectric above the floating gate.

8. The array of claim 1, wherein each memory device of the three dimensional array comprises:

a source region, a channel region and a drain region each vertically aligned with one another to form a pillar;

a first electrode contacting the source region;

a second electrode contacting the drain regions;

a charge storage region located adjacent to and in contact with the channel region; and

a control gate located adjacent to and in direct contact with the charge storage region.

9. The array of claim 1, wherein the array of nonvolatile memory devices comprises an array of TFT EEPROMs.

10. The array of claim 9, wherein the array comprises:

a plurality of vertically separated device levels, each level comprising an array of TFT EEPROMs, each TFT EEPROM comprising a channel, source and drain regions, a control gate, and a charge storage region between the channel and the control gate;

a plurality of bit line columns in each device level, each bit line contacting the source or the drain regions of the TFT EEPROMs;

a plurality of word line rows in each device level; and

at least one interlayer insulating layer located between the device levels.

11. The array of claim 10, wherein:

the channel of each TFT EEPROM comprises amorphous silicon or polysilicon;

the columns of bit lines extend substantially perpendicular to a source-channel-drain direction of the TFT EEPROMs;

each word line contacts the control gates of the TFT EEPROMs, and the rows of word lines extend substantially parallel to the source-channel-drain direction of the TFT EEPROMs; and

the word lines are self aligned to the control gates of the array of TFT EEPROMs and the word lines are self aligned to the channel and the charge storage regions of the TFT EEPROMs located below the respective word lines.

12. The array of claim 1, wherein the array of nonvolatile memory devices comprises a flash memory array which is programmed by FN tunneling.

13. The array of claim 12, wherein the array comprises:

a first plurality of spaced-apart conductive bit lines disposed at a first height above the substrate in a first direction; and

a second plurality of spaced-apart rail-stacks disposed at a second height in a second direction different from the first direction, each rail-stack including a plurality of semiconductor islands whose first surface is in contact with said first plurality of spaced-apart conductive bit lines, a conductive word line, and charge storage regions disposed between a second surface of the semiconductor islands and the word line.

14. A nonvolatile memory my, comprising:

an array of nonvolatile memory devices;

at least one driver circuit; and

a substrate;

wherein the at least one driver circuit is not located in a bulk monocrystalline silicon substrate, wherein the array of nonvolatile memory devices comprises an array of PROMs, EPROMs or EEPROMs, wherein the array comprises;

a first plurality of spaced-apart conductors disposed at a first height above the substrate in a first direction; and

a second plurality of spaced-apart rail-stacks disposed above the first height in a second direction different from the first direction, each rail-stack including a semiconductor film of a first conductivity type in contact with said first plurality of spaced-apart conductors, a local charge storage film disposed above the semiconductor film and a conductive film disposed above the local charge storage film.

15. The array of claim 14, wherein:

a space between said spaced-apart conductors contains a planarized deposited oxide material;

said semiconductor film comprises polysilicon; and

said local charge storage film is selected from a group consisting of a dielectric isolated floating gate, an ONO dielectric film and an insulating layer containing conductive nanocrystals.

16. A nonvolatile memory array, comprising:

a monocrystalline silicon substrate;

at least one driver circuit formed above the substrate; and

an array of nonvolotile memory devices formed above the substrate,

wherein the array of nonvolotile memory devices comprises a monolithic three dimentional array of memory devices.

17. The array of claim 16, wherein the array of nonvolatile memory devices comprises a three dimensional array of antifuses.

18. The array of claim 17, wherein the array of antifuses comprise a first set of rail stack conductors, a second set of rail stack conductors extending in a different direction than the first set of rail stack conductors, and an insulating layer disposed between the first and the second sets of rail stacks.

19. The array of claim 18, further comprising semiconductor diodes located at intersections of the conductors of the first and the second sets of rail stacks.

20. The array of claim 19, wherein the diodes comprise P+/N−

diodes.