Method for erasing a memory cell

• US 6,888,757 B2
• Filed: 09/08/2003
• Issued: 05/03/2005
• Est. Priority Date: 10/24/2001
• Status: Expired due to Term

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Lusky, Eli
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US10/656,251
• Publication Number:
  US 20040047198A1
• Time in Patent Office: 603 Days
• Field of Search: 365/185.22, 365/185.19, 365/185.2, 365/185.29, 365/194
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A method for erasing a bit of a memory cell in a non-volatile memory cell array, the method comprising applying an erase pulse to at least one bit of at least one memory cell of the array, waiting a delay period wherein a threshold voltage of the at least one memory cell drifts to a different magnitude than at the start of the delay period, and after the delay period, erase verifying the at least one bit to determine if the at least one bit is less than a reference voltage level.

Claims

1. A method for erasing a bit of a memory cell in a non-volatile memory cell array, the method comprising:

applying an erase pulse to at least one bit of at least one memory cell of said array;

waiting a delay period wherein a threshold voltage of said at least one memory cell drifts to a different magnitude than at the start of the delay period; and

after said delay period, erase verifying said at least one bit to determine if said at least one bit is less than a reference voltage level.

2. The method according to claim 1, wherein said delay period is determined as a function of prior threshold voltage drift behavior of at least one similar memory cell.

3. The method according to claim 1, wherein during said delay period, an environmental condition of said at least one memory cell remains generally unchanged.

4. The method according to claim 1, further comprising changing an environmental condition of said at least one memory cell during said delay period.

5. The method according to claim 4, wherein said environmental condition comprises at least one of temperature, pressure, and humidity.

6. The method according to claim 1, wherein an erase condition used to erase said at least one memory cell remains generally unchanged throughout said delay period.

7. The method according to claim 1, further comprising changing an erase condition used to erase said at least one memory cell after said delay period has started.

8. The method according to claim 7, wherein said erase condition comprises at least one of a gate voltage, a drain voltage, a source voltage, and a time duration of an erase pulse.

9. The method according to claim 1, wherein said at least one memory cell comprises a channel formed in a substrate, two diffusion areas formed one on either side of said channel in said substrate, and an oxide-nitride-oxide (ONO) layer formed at least over said channel, said ONO layer comprising a bottom oxide layer, a top oxide layer and a nitride layer intermediate said bottom and top oxide layers, and wherein said delay period is determined as a function of the thickness of said bottom layer.

10. The method according to claim 1, wherein if a threshold voltage of said at least one bit is not less than said reference voltage level, at least one more erase pulse is applied to said at least one bit.

11. The method according to claim 1, wherein if a threshold voltage of said at least one bit is less than said reference voltage level, at least one more erase pulse is applied to said at least one bit.

12. A non-volatile memory cell array comprising:

a plurality of memory cells;

a power supply adapted to generate erase pulses to bits of said cells; and

a controller in communication with said power supply, said controller adapted to perform the steps of;

applying an erase pulse to at least one bit of at least one memory cell of said array;

waiting a delay period wherein a threshold voltage of said at least one memory cell drifts to a different magnitude than at the start of the delay period; and

after said delay period, erase verifying said at least one bit to determine if said at least one bit is less than a reference voltage level.

13. The array according to claim 12, wherein said memory cells comprise nitride read only memory (NROM) cells.