Wireless communication device with phase-locked loop oscillator
First Claim
1. A programmable high speed counter apparatus, comprising:
- a prescaler having a prescaler clock input, first and second control inputs, and a prescaler output clock having a quad-modulus counter with a divide ratio determined by the first and second control inputs, an integer portion of the divide ratio based in part on the first control input and a fractional portion of the divide ratio based in art on the second control input; and
first, second and third programmable counters each having programmable counter inputs to receive data indicative of a respective count value and a clock input coupled to the prescaler output clock, the first control input having a first logic level while the second counter is in a non-zero stale and the second control input having the first logic level while the third counter is in a non-zero state.
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Accused Products
Abstract
A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting stages are used to generate the first and second modulus control signals. The first modulus control signal is at a first logic level when the associated counter is at a non-zero value and is at a second logic level when the associated counter reaches zero. The second modulus control signal is generated by a second counter and has a first logic value when the second counter is in a non-zero state and a second logic value when the second counter reaches zero.
28 Citations
37 Claims
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1. A programmable high speed counter apparatus, comprising:
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a prescaler having a prescaler clock input, first and second control inputs, and a prescaler output clock having a quad-modulus counter with a divide ratio determined by the first and second control inputs, an integer portion of the divide ratio based in part on the first control input and a fractional portion of the divide ratio based in art on the second control input; and
first, second and third programmable counters each having programmable counter inputs to receive data indicative of a respective count value and a clock input coupled to the prescaler output clock, the first control input having a first logic level while the second counter is in a non-zero stale and the second control input having the first logic level while the third counter is in a non-zero state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A programmable high speed counter apparatus, comprising:
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a prescaler having a prescaler clock input, a plurality of control inputs, and a prescaler output clock having a modulus determined by the plurality of control inputs, the modulus capable of fractional values; and
a plurality of programmable counters each having programmable counter inputs to receive data indicative of a respective count value and a clock input coupled to the prescaler output clock, a first counter of the plurality of programmable counters generating a preset signal to program the programmable counter inputs and the remaining ones of the programmable counters each controlling one of the control inputs with each control input having a first logic level while the respective counter is in a non-zero state and a second logic level while the respective counter is in a zero state. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A programmable high speed frequency generator apparatus, comprising:
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first counter means having an input and an output whose count modulus, configurable from a plurality of integer and fractional values, is determined by a plurality of control inputs; and
second counter means having a plurality of counter stages each having programmable counter inputs to receive data indicative of a respective count value and a clock input coupled to the output of the first counter means, a first counter of the plurality of counter stages generating a preset signal to program the programmable counter inputs, the remaining ones of the plurality of counter stages each controlling one of the control inputs for the first counter means. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A method for frequency generation comprising:
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supplying a clock signal to a programmable modulus counter whose count modulus, configurable to an integer or a fractional value, is determined by a plurality of control inputs;
programing each of a plurality of counter stages with a respective count value; and
supplying an output signal from the modulus counter to the plurality of counter stages wherein the programming of the plurality of counter stages is based on a count value of a first counter of the plurality of counter stages and the control inputs for the modulus counter are based on count values of respective ones of the remaining ones of the plurality of counter stages. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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36. A programmable high speed counter apparatus, comprising:
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a prescaler having a prescaler clock input, first and second control inputs, and a prescaler output clock having a quad-modulus counter with a divide ratio determined by the first and second control inputs; and
first, second and third programmable counters each having programmable counter inputs to receive data indicative of a respective count value and a clock input coupled to the prescaler output clock, the first control input having a first logic level while the second counter is in a non-zero state and the second control input having the first logic level while the third counter is in a non-zero state;
wherein the divide ratio of the quad modulus counter generates divide ratios having the following relationship;
P, P+1, P+√
{square root over (P)}, and P+√
{square root over (P)}+1 depending on the logic state of the first and second control inputs. - View Dependent Claims (37)
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Specification