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Wireless communication device with phase-locked loop oscillator

  • US 6,888,913 B2
  • Filed: 07/02/2002
  • Issued: 05/03/2005
  • Est. Priority Date: 07/02/2002
  • Status: Active Grant
First Claim
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1. A programmable high speed counter apparatus, comprising:

  • a prescaler having a prescaler clock input, first and second control inputs, and a prescaler output clock having a quad-modulus counter with a divide ratio determined by the first and second control inputs, an integer portion of the divide ratio based in part on the first control input and a fractional portion of the divide ratio based in art on the second control input; and

    first, second and third programmable counters each having programmable counter inputs to receive data indicative of a respective count value and a clock input coupled to the prescaler output clock, the first control input having a first logic level while the second counter is in a non-zero stale and the second control input having the first logic level while the third counter is in a non-zero state.

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