Method and apparatus for supporting SDRAM memory

• US 6,889,284 B1
• Filed: 10/19/1999
• Issued: 05/03/2005
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Foo, Khong S., Nizar, Puthiya K.
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US09/420,887
• Time in Patent Office: 2,023 Days
• Field of Search: 711/105, 711/202, 711/154, 710/305, 710/306, 710/316, 710/315, 709/250
• US Class Current: 710/315
• CPC Class Codes: G06F 13/4004 Coupling between buses
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A memory translation hub comprising a memory channel interface, a memory bus interface, and a command generator coupled to the memory channel interface and to the memory bus interface. The memory channel interface receives a memory control packet from a memory channel. The memory bus interface provides a memory bus. The command generator causes the memory bus interface to provide memory control signals on the memory bus responsive to the memory control packet.

Claims

1. A memory translation hub comprising:

a memory bus interface that provides a memory bus having a memory bus cycle time;

a memory channel interface that receives a memory control packet from a memory channel that times transmission of the memory control packet based on the memory bus cycle time, wherein the memory control packet includes command flag bits that indicate that the memory control packet is one of an activate command, a read/write command, and an extended command, the command flag bits being the first bits in the memory control packet; and

a command generator coupled to the memory channel interface and to the memory bus interface, the command generator causing the memory bus interface to provide memory control signals on the memory bus responsive to the memory control packet.

2. The memory translation hub of claim 1 wherein the memory channel includes a control portion and a data portion, the memory channel interface receiving a memory control packet only from the control portion of the memory channel.

3. The memory translation hub of claim 1 wherein the memory control packet specifies a memory row, a memory row address, a memory bank address, and a device identification mask if the memory control packet is the activate command.

4. The memory translation hub of claim 1 wherein the memory control packet specifies a memory row, a memory column address, and a memory bank address, if the memory control packet is the read/write command.

5. The memory translation hub of claim 1 wherein, if the memory control packet is the extended command, the memory control packet includes extended flag bits that indicate that the memory control packet is one of a retire with mask command, a pre-charge command, and a service command.

6. The memory translation hub of claim 5 wherein the memory control packet specifies a memory row, and a byte mask, if the memory control packet is the retire with mask command.

7. The memory translation hub of claim 5 wherein the memory control packet specifies a memory row, and one of a broadcast flag and a memory bank address, if the memory control packet is the pre-charge command.

8. The memory translation hub of claim 5 wherein the memory control packet specifies a memory row, an operation, and one of a broadcast flag and a memory bank address, if the memory control packet is the service command.

9. The memory translation hub of claim 8 wherein the operation is one of a no operation, refresh, self refresh entry, self refresh exit, power-down entry, power-down exit, clock stop, current calibrate and sample, and temperature calibrate.

10. The memory translation hub of claim 2 further comprising a write logic circuit coupled to the memory channel interface and to the memory bus interface, the write logic circuit receiving a write data packet from the memory channel interface and causing the memory bus interface to provide memory control signals and data signals on the memory bus representative to the write data packet, the memory channel interface receiving a write data packet only from the data portion of the memory channel.

11. The memory translation hub of claim 2 further comprising a read logic circuit coupled to the memory channel interface and to the memory bus interface, the read logic circuit receiving read data from the memory bus interface, generating a read data packet containing the read data, and causing the memory channel interface to transmit the read data packet on the data portion of the memory channel.

12. A memory translation hub comprising:

means for receiving a memory control packet from a memory channel with a timing based on a cycle timing of a memory bus, wherein the memory control packet includes command flag bits that indicate that the memory control packet is one of an activate command, a read/write command, and an extended command, the command flag bits being the first bits in the memory control packet;

means for translating the memory control packet to memory control signals; and

means for generating the memory control signals on the memory bus.

13. The memory translation hub of claim 12 wherein the means for receiving a memory control packet further comprises means for receiving a memory control packet from a control portion of the memory channel responsive to the memory control packet.

14. The memory translation hub of claim 13 further comprising:

means for receiving a write data packet from a data portion of the memory channel;

means for providing memory control signals and data signals on the memory bus responsive to the write data packet.

15. The memory translation hub of claim 13 further comprising:

means for receiving read data from the memory bus;

means for generating a read data packet containing the read data; and

means for transmitting the read data packet on a data portion of the memory channel.

16. A method of connecting a memory bus to a memory controller hub through a memory channel comprising:

receiving a memory control packet from the memory channel, timing of receiving the memory control packet being based on a cycle timing of the memory bus, wherein the memory control packet includes command flag bits that indicate that the memory control packet is one of an activate command, a read/write command, and an extended command, the command flag bits being the first bits in the memory control packet;

translating the memory control packet to memory control signals; and

generating the memory control signals on the memory bus.

17. The method of claim 16 further comprising:

receiving a write data packet from the memory channel; and

providing memory control signals and data signals on the memory bus responsive to the write data packet.

18. The method of claim 16 further comprising:

receiving read data from the memory bus interface;

generating a read data packet containing the read data; and

transmitting the read data packet on the memory channel.

19. A memory subsystem comprising:

a memory bus having a memory bus cycle time;

a memory device coupled to the memory bus;

a memory channel;

a memory control hub coupled to the memory channel, the memory control hub transmitting memory control packets based on the memory bus cycle time, wherein memory control packets include command flag bits that indicate that each of the memory control packets is one of an active command, a read/write command, and an extended command, the command flag bits being the first bits in each of the memory control packets; and

a memory translation hub coupled to the memory channel and to the memory bus, the memory translation hub to receive a memory control packet from the memory channel, and to generate memory control signals on the memory bus responsive to the memory control packet.

20. The memory subsystem of claim 19 wherein the memory channel includes a control portion and a data portion, the memory translation hub receiving a memory control packet only from the control portion of the memory channel.

21. The memory subsystem of claim 20 wherein the memory translation hub further receives a write data packet from the data portion of the memory channel, and generates memory control signals and data signals on the memory bus responsive to the write data packet.

22. The memory translation hub of claim 20 wherein the memory translation hub further receives read data from the memory bus interface, generates a read data packet containing the read data, and transmits the read data packet on the data portion of the memory channel.