Memory device supporting a dynamically configurable core organization

• US 6,889,304 B2
• Filed: 11/22/2002
• Issued: 05/03/2005
• Est. Priority Date: 02/28/2001
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Stark, Donald C., Ware, Frederick A.
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): ROJAS, MIDYS
• Application Number:
  US10/302,420
• Publication Number:
  US 20040019756A1
• Time in Patent Office: 893 Days
• Field of Search: 711/115, 711/170, 711/5
• US Class Current: 711/170
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1087 : Data input latches
• CPC Class Codes: G11C 8/06 : Address interface arrangements, e.g. address buffers
• CPC Class Codes: H05K 1/117 : Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 1/14 : Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 2201/09954 : More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
• CPC Class Codes: H05K 2201/10189 : Non-printed connector
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Claims

1. A memory system comprising:

a. a memory bus having a plurality of system data lines; and

b. at least one memory module having;

i. a plurality of module pins connected to respective ones of the system data lines;

ii. a plurality of memory banks;

iii. configuration and control logic connected to the memory banks and adapted to configure the memory banks to form one of several memory-width configurations; and

iv. a switch matrix connected between the memory banks and the plurality of module pins, the switch matrix adapted to programmably connect the memory banks to all or a subset of the system data pins;

c. wherein doubling the number of memory modules in the system automatically halves the memory-width configuration for each module.

2. A memory system comprising:

a. a first address bus;

b. a second address bus;

c. a first memory bank, including a first address port connected to the first address bus, a first memory array, and a first sense amplifier;

d. a second memory bank, including a second address port connected to the first and second address busses, a second memory array, and a second sense amplifier; and

e. configuration and control logic connected to the memory banks and adapted to configure the memory system in one of at least two addressing modes, including a first addressing mode and a second addressing mode;

f. wherein the memory system moves first data from a first address in the first memory array to the first sense amplifier and moves second data from a second address in the second memory array to the second sense amplifier in the first addressing mode, the first and second addresses being selected using the first address bus; and

g. wherein the memory system moves third data from a third address in the first memory array to the first sense amplifier and moves fourth data from a fourth address in the second memory array to the second sense amplifier in the second addressing mode, wherein the third and fourth addresses are separate addresses selected using the respective first and second address busses.

3. The memory system of claim 2, further comprising a memory access bus including first and second data lines, wherein the first and second data are provided substantially simultaneously on the respective first and second data lines and the third and fourth data are provided substantially on the respective first and second data lines.

4. The memory system of claim 2, further comprising a memory access bus including first and second data lines, wherein the first and second data are provided substantially simultaneously on the respective first and second data lines and the third data is provided on the first data line before the fourth data is provided on the second data line.

5. A memory component comprising:

a. a first memory bank having a first memory array and a first sense amplifier;

b. a second memory bank having a second memory array and a second sense amplifier;

c. configuration logic connected to the first and second memory banks, the configuration logic supporting at least first and second memory-access modes;

i. wherein the configuration logic loads first data from the first memory array into the first sense amplifier and substantially simultaneously loads second data from the second memory array into the second sense amplifier in the first memory-access mode; and

ii. wherein the configuration logic sequentially loads the first data from the first memory array into the first sense amplifier and the second data from the second memory array into the second sense amplifier in the second memory-access mode.

6. The memory component of claim 5, further comprising first and second data terminals and data control circuitry, wherein the data control circuitry is adapted to transfer the first and second data substantially simultaneously in the respective first and second sense amplifiers to the first and second data terminals in the first memory-access mode.

7. The memory component of claim 5, further comprising first and second data terminals and data control circuitry, wherein the data control circuitry is adapted to sequentially transfer the first and second data in the respective first and second sense amplifiers to the first data terminal in the second memory-access mode.

8. The memory component of claim 5, wherein the first data is stored at a first address in the first memory array, the second data is stored at a second address in the second memory array, and wherein the first and second addresses differ.

9. A memory component comprising:

a. first and second data terminals;

b. first and second memory arrays;

c. configuration and switching logic connected between the data terminals and the memory arrays, the configuration and switching logic supporting at least first and second memory-access modes;

i. wherein the configuration and switching logic, substantially simultaneously, transfers first data from the first memory array to the first data terminal and transfers second data from the second memory array to the second data terminal in the first memory-access mode; and

ii. wherein the configuration and switching logic sequentially transfers the first data from the first memory array to the first data terminal and the second data from the second memory array to the first data terminal in the second memory-access mode.

10. The memory component of claim 9, further comprising a first memory output latch disposed between the first memory array and the configuration and switching logic and a second memory output latch disposed between the second memory array and the configuration and switching logic.

11. The memory component of claim 10, further comprising a first sense amplifier disposed between the first memory output latch and the first memory array and a second sense amplifier disposed between the second memory output latch and the second memory array.

12. The memory component of claim 11, wherein the configuration and switching logic transfers, substantially simultaneously, the first data from the first memory array to the first sense amplifier and transfers the second data from the second memory array to the second sense amplifier before transferring, substantially simultaneously, the first data from the first sense amplifier to the first data terminal and transferring the second data from the second sense amplifier to the second data terminal in the first memory-access mode.

13. The memory component of claim 11, wherein the configuration and switching logic transfers, substantially simultaneously, the first data from the first memory array to the first sense amplifier and transfers the second data from the second memory array to the second sense amplifier before sequentially transferring the first data from the first sense amplifier to the first data terminal and transferring the second data from the second sense amplifier to the second data terminal in the first memory-access mode.

14. The memory component of claim 10, further comprising a mode register connected to the configuration and switching logic and adapted to define whether the memory component operations in the first memory-access mode of the second memory-access mode.