Microprocessor and program modification method in the microprocessor

• US 6,889,306 B1
• Filed: 10/27/2000
• Issued: 05/03/2005
• Est. Priority Date: 10/29/1999
• Status: Expired due to Term

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tani, Takenobu
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/697,429
• Time in Patent Office: 1,649 Days
• Field of Search: 711/202, 711/102, 711/103, 711/208, 711/220, 711/3, 713/1, 713/2, 713/100, 717/168, 717/169, 717/122, 365/236, 365/230.02, 712/203, 712/223, 712/205, 712/229, 712/230, 712/235, 712/245, 712/37
• US Class Current: 711/202
• CPC Class Codes: G06F 9/268 Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs

Abstract

The microprocessor is provided with a program modification function not attended with unnecessary branch instructions or interrupt processes. The instruction storage unit includes read-only-memory (ROM) for storing instructions composing a program to be processed and a modified instruction storage unit for storing modified instructions for program modification. When the upper bits of an instruction address supplied from the program counter match with the upper bits of the modifying address, the address translation unit translates the upper bits of the instruction address into the upper bits of the substitutive address where the modified instruction is stored in the modified instruction storage unit.

Claims

1. A microprocessor provided with a program modification function comprising:

an instruction storage unit including a read-only-memory (ROM) for storing instructions composing a program to be processed and a modified instruction storage unit for storing a modified instruction for program modification; and

an address translation unit for receiving an instruction address of an instruction stored in said ROM and for translating the instruction address into a substitutive address at which the modified instruction is stored in said modified instruction storage unit when the instruction address matches with a modifying address which is an address of an instruction to be modified,

said address translation unit outputting the substitutive address to said instruction storage unit instead of the instruction address, wherein said address translation unit is so composed that a bit width to be a translation target is changeable when the instruction address is translated into the substantive address,

wherein said address translation unit comprises;

a modifying address storage unit for holding a value of a predetermined bit of the modifying address;

an address comparator for comparing a value of said predetermined bit of the instruction address with the value held in said modifying address storage unit to determine whether or not these values match with each other;

a substitutive address storage unit for holding a value of said predetermined bit of said substitutive address;

an address selector for receiving determination results of said address comparator, outputting as a value of said predetermined bit of a new instruction address, the value held in said substitutive address storage unit when the received results indicate that these values match with each other, and otherwise, the value of said predetermined bit of the instruction address; and

a translation range setting means capable of setting whether or not said predetermined bit is designated as a translation target bit, said translation range setting means making said address selector output the value of said predetermined bit of the instruction address, regardless of the determination results of said address comparator when said predetermined bit is not designated as the translation target bit.

2. A microprocessor provided with a program modification function comprising:

an instruction storage unit including a read-only-memory (ROM) for storing instructions composing a program to be processed and a modified instruction storage unit for storing a modified instruction for program modification; and

an address translation unit for receiving an instruction address of an instruction stored in said ROM and for translating the instruction address into a substitutive address at which the modified instruction is stored in said modified instruction storage unit when the instruction address matches with a modifying address which is an address of an instruction to be modified,

said address translation unit outputting the substitutive address to said instruction storage unit instead of the instruction address,

wherein, said address translation unit comprises;

a modifying address storage unit for holding a value of a predetermined bit of the modifying address;

an address comparator for comparing a value of said predetermined bit of the received instruction address with the value held in said modifying address storage unit to determine whether or not these values match with each other;

a substitutive address storage unit for holding a value of said predetermined bit of the substitutive address; and

an address selector for receiving determination results of said address comparator, outputting as a value of said predetermined bit of a new instruction address, the value held in said substitutive address storage unit when the received results indicate that these values match with each other, and otherwise, the value of said predetermined bit of the instruction address.