Integrated circuit incorporating dual organization memory array

• US 6,889,307 B1
• Filed: 11/16/2001
• Issued: 05/03/2005
• Est. Priority Date: 11/16/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/990,901
• Time in Patent Office: 1,264 Days
• Field of Search: 711/202, 711/212, 711/220
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A memory organization supports a basic page size and an extended page size. A certain portion of its memory cells are dual-addressable memory cells which may be used to provide the additional memory required for the extended pages or alternatively may be used to provide additional memory within a basic page. A memory array is preferably implemented as basic pages and directly addressed to support the basic page size. The received addresses are translated to map each extended page into a portion of a basic page to support the extended pages. In one embodiment, high order row addresses are conveyed for use as high-order column addresses, and the high-order row addresses overridden, to map each extended page into a contiguous block of basic pages.

Claims

1. An integrated circuit comprising:

a memory array organized in pages of a first width, which memory array is addressable as pages of the first width and addressable as pages of a second width that is an additional width greater than the first width;

wherein, when addressable as pages of the second width, the additional width of each page of the second width is mapped into at least one associated page of the first width.

2. The integrated circuit defined in claim 1 wherein:

when addressed as pages of the second width, each respective page is addressable as a respective basic page of the first width and as a respective extended page of a width smaller than the first width.

3. The integrated circuit defined in claim 2 wherein:

when addressed as pages of the second width, the memory array is configured to map each extended page into a corresponding portion of a corresponding basic page.

4. The integrated circuit defined in claim 1 wherein:

the memory array, when first addressed as pages of the second width, is configured to map the additional width of each respective page of the second width into a respective associated page of the first width.

5. The integrated circuit defined in claim 4 wherein the memory array is accessed byte-serially by page.

6. The integrated circuit defined in claim 1 wherein:

the memory array comprises a non-volatile memory array.

7. The integrated circuit defined in claim 6 wherein:

the memory array comprises a three-dimensional memory array.

8. The integrated circuit defined in claim 6 wherein:

the non-volatile memory array comprises passive element memory cells.

9. The integrated circuit defined in claim 1 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.

10. An integrated circuit comprising:

a memory array organized as a plurality of pages having a page width;

an address translation block for translating an address of an effective location within a page that falls beyond the page width, into a corresponding address of a corresponding location of a corresponding page that falls within the page width, thereby mapping an effective page location beyond its page width into an associated page.

11. The integrated circuit defined in claim 10 wherein:

the address translation block is arranged to map at least one address bit that specifies a page into an address bit specifying a location within an associated page.

12. The integrated circuit defined in claim 10 wherein:

the address translation block is arranged to map effective locations within the pages beyond the page width into a contiguous group of pages located at one end of the memory array.

13. The integrated circuit defined in claim 10 wherein:

the page width is equal to a first integral power of two; and

the number of mapped locations of each page is equal to a second integral power of two.

14. The integrated circuit defined in claim 13 wherein:

the first integral power of two is not equal to the second integral power of two.

15. The integrated circuit defined in claim 14 wherein the memory array is accessed byte-serially by page.

16. The integrated circuit defined in claim 10 wherein:

the memory array comprises a non-volatile memory array.

17. The integrated circuit defined in claim 10 wherein:

the memory array comprises a plurality of sub-arrays.

18. The integrated circuit defined in claim 10 wherein:

the memory array comprises at least one sub-array, each of which includes a plurality of memory cells, each coupled to a respective one of a plurality of first array terminal lines and coupled to a respective one of a plurality of second array terminal lines; and

the first page width is smaller than the number of memory cells respectively coupled to each of the plurality of first array terminal lines.

19. The integrated circuit defined in claim 10 wherein:

the memory array comprises at least one sub-array, each of which includes a plurality of memory cells, each coupled to a respective one of a plurality of first array terminal lines and coupled to a respective one of a plurality of second array terminal lines; and

the first page width is greater than or equal to the number of memory cells respectively coupled to each of the plurality of first array terminal lines.

20. The integrated circuit defined in claim 10 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.

21. An integrated circuit comprising:

a memory array organized as a plurality of at least 2^D pages, each of width 2^W; and

an address translation block for translating an address that references an effective location within a page that is greater than its page width 2^W by up to an additional width 2^X, into a corresponding address that references a corresponding location within a corresponding page of width 2^W;

wherein D, W, and X are non-negative integers, W is greater than X, and D is greater than (W−

X).

22. The integrated circuit defined in claim 21 wherein:

the memory array is addressable as at least 2^D−

2<sup>D−

(W−

X)</sup> pages of width 2^W+2^X, each such page comprising a basic page of width 2^W and an extended page of width 2^X; and

the address translation block is configured to map the 2^D extended pages of width 2^X into a group of 2<sup>D−

(W−

X)</sup> basic pages of width 2^W.

23. The integrated circuit defined in claim 22 wherein:

the group of 2<sup>D−

(W−

X)</sup> basic pages into which the extended pages are mapped are contiguous pages located at one end of the memory array.

24. The integrated circuit defined in claim 23 wherein:

the respective extended pages of a plurality of adjacent pages are mapped into a single basic page.

25. The integrated circuit defined in claim 23 wherein:

the memory array comprises a non-volatile memory array.

26. The integrated circuit defined in claim 25 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.

27. The integrated circuit defined in claim 22 wherein:

the group of 2<sup>D−

(W−

X)</sup> basic pages into which the extended pages are mapped are non-contiguous pages comprising at least two groups of at least one page per group within the memory array.

28. The integrated circuit defined in claim 22 wherein:

X is within the range 3 to 5; and

W is within the range 6 to 12.

29. The integrated circuit defined in claim 22 wherein:

when an extended page is first addressed, the 2^D extended pages of width 2^X are mapped into a group of 2<sup>D−

(W−

X)</sup> basic pages of width 2^W; and

otherwise, said group of 2<sup>D−

(W−

X)</sup> basic pages of width 2^W are addressable in like fashion as other basic pages, thereby providing at least 2^D addressable basic pages of width 2^W.

30. The integrated circuit defined in claim 29 wherein the memory array is accessed byte-serially by page.

31. The integrated circuit defined in claim 21 wherein:

the memory array comprises a non-volatile memory array of passive element memory cells.

32. The integrated circuit defined in claim 21 wherein:

the memory array comprises a plurality of sub-arrays.

33. The integrated circuit defined in claim 21 wherein:

each page location comprises a plurality of memory cells.

34. The integrated circuit defined in claim 33 wherein:

the plurality of memory cells comprising each page location are distributed among at least two sub-arrays.

35. The integrated circuit defined in claim 33 wherein:

the plurality of memory cells comprising each page location are disposed in a single sub-array.

36. The integrated circuit defined in claim 21 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.

37. The integrated circuit defined in claim 21 wherein the memory array is accessed byte-serially by page.

38. An integrated circuit comprising:

a memory array having at least 2^M rows and having 2^N columns of memory locations, but which is addressable as rows having more than 2^N columns;

wherein a location having a column address greater than 2^N is mapped into an associated location of an associated row, having a column address no larger than 2^N; and

wherein M and N positive integers.

39. The integrated circuit defined in claim 38 further comprising:

an address translation block for translating an address having a row address portion up to 2^M and having a column address portion greater than 2^N by up to an additional 2^X, into a corresponding address having a corresponding row address portion and having a corresponding column address portion no greater than 2^N.

40. The integrated circuit defined in claim 39 wherein:

the memory array is addressable as at least 2^M−

2<sup>M−

(N−

X)</sup> rows, each having 2^N+2^X, columns; and

the address translation block is configured to map the upper 2^X addressable columns of each of the 2^M rows into a group of 2<sup>M−

(N−

X)</sup> rows each having 2^N columns.

41. The integrated circuit defined in claim 40 wherein:

the group of 2<sup>M−

(N−

X)</sup> rows into which the upper 2^X addressable columns are mapped are contiguous rows located at one end of the memory array.

42. The integrated circuit defined in claim 40 wherein:

the group of 2<sup>M−

(N−

X)</sup> rows into which the upper 2^X addressable columns are mapped are non-contiguous rows comprising at least two groups of at least one row per group within the memory array.

43. The integrated circuit defined in claim 40 wherein:

X is within the range 3 to 5; and

N is within the range 6 to 12.

44. The integrated circuit defined in claim 38 wherein:

the memory array comprises a non-volatile memory array.

45. The integrated circuit defined in claim 38 wherein:

the memory array comprises a plurality of sub-arrays.

46. The integrated circuit defined in claim 38 wherein:

each memory location comprises a plurality of memory cells distributed among at least two memory sub-arrays.

47. An integrated circuit comprising:

a memory array addressable as a plurality P1 of pages of a width S1 defining a corresponding number of bits N1, and also addressable as a plurality P2 of pages of a width S2 defining a corresponding number of bits N2;

wherein P1 is not equal to P2, S1 is not equal to one-half of S2, and S1 is not equal to S2.

48. The integrated circuit defined in claim 47 wherein:

N1 substantially equals N2.

49. The integrated circuit defined in claim 47 wherein:

S1 is an integral power of two;

S2 is not an integral power of two; and

S2 is larger than S1.

50. The integrated circuit defined in claim 49 wherein:

(S2-S1) is an integral power of two.

51. The integrated circuit defined in claim 49 wherein:

S1 is equal to 512 bytes; and

S2 is equal to 528 bytes.

52. The integrated circuit defined in claim 49 wherein:

the memory is configured to be addressable only as page width S2 when such larger page width is first addressed.

53. The integrated circuit defined in claim 49 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.

54. The integrated circuit defined in claim 47 wherein:

the memory comprises a plurality of non-volatile memory sub-arrays; and

the memory is configured to store more than one bit at each page location.

55. The integrated circuit defined in claim 47 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.

56. An integrated circuit comprising:

a memory array of memory cells organized in pages, which memory array is addressable in a first mode as pages of a first width and addressable in a second mode as pages of a second width greater than the first width;

wherein the array is initially addressable in the first mode until a page larger than said first width is first addressed, and is then addressable only in the second mode; and

wherein substantially every memory cell that is addressable in one of the first and second modes is also addressable in the other mode.

57. The integrated circuit defined in claim 56 wherein:

at least one of the first width and second width is not an integral power of two.

58. The integrated circuit defined in claim 56 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.

59. The integrated circuit defined in claim 56 wherein the memory array is accessed byte-serially by page.

60. An integrated circuit comprising:

a three-dimensional memory array having more than one plane of memory cells, said memory array having at least a number R of rows and having at least a number C of columns of memory locations, having at least some dually-addressable memory locations, each said dually-addressable memory location being addressable at a respective first row address and respective first column address, and also addressable at a respective second row address and respective second column address;

wherein the respective first row address is different than the respective second row address, and the respective first column address is different than the respective second column address, for at least one dually-addressable memory location.

61. The integrated circuit defined in claim 60 wherein:

each dually-addressable memory location, once any of such locations is addressed at its respective second row address and respective second column address, is configured to only be addressable at its respective second row address and respective second column address.

62. The integrated circuit defined in claim 61 wherein:

the memory array comprises non-volatile passive element memory cells.

63. The integrated circuit defined in claim 61 wherein the memory array is accessed byte-serially by page.

64. An integrated circuit comprising:

a three dimensional memory array having more than one plane of memory cells, said memory array addressable as a plurality P1 of pages of a width S1 defining a corresponding number of bits N1, and also addressable as a plurality P2 of pages of a width S2 defining a corresponding number of bits N2;

wherein P1 is not equal to P2, and S1 is not equal to S2.

65. The integrated circuit defined in claim 64 wherein:

S1 is an integral power of two;

S2 is not an integral power of two; and

S2 is larger than S1.

66. The integrated circuit defined in claim 65 wherein:

(S2-S1) is an integral power of two.

67. The integrated circuit defined in claim 65 wherein:

the memory array is configured to be addressable only as page width S2 when such larger page width is first addressed.

68. The integrated circuit defined in claim 67 wherein the memory array is accessed byte-serially by page.

69. The integrated circuit defined in claim 64 wherein:

the memory array comprises a plurality of non-volatile memory sub-arrays; and

the memory array is configured to store more than one bit at each page location.

70. An integrated circuit comprising:

a memory array addressable as a plurality P1 of pages of a width S1 defining a corresponding number of bits N1, and also addressable as a plurality P2 of pages of a width S2 defining a corresponding number of bits N2;

wherein P1 is not equal to P2, and S1 is not equal to S2; and

wherein the memory array comprises a plurality of non-volatile memory sub-arrays; and

wherein the memory array is configured to store more than one bit at each page location.

71. The integrated circuit defined in claim 70 wherein:

S1 is an integral power of two;

S2 is not an integral power of two; and

S2 is larger than S1.

72. The integrated circuit defined in claim 71 wherein:

(S2-S1) is an integral power of two.

73. The integrated circuit defined in claim 71 wherein:

the memory array is configured to be addressable only as page width S2 when such larger page width is first addressed.

74. The integrated circuit defined in claim 73 wherein the memory array is accessed byte-serially by page.