Method and apparatus for entering and exiting multiple threads within a multithreaded processor
First Claim
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1. A method including:
- maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status of an associated thread of multiple threads being executed with a multithreaded processor;
detecting a change of status for a first thread within the multithreaded processor; and
responsive to the change of status for the first thread within the multithreaded processor, configuring a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine, wherein the configuring of the functional unit within the multithreaded processor includes inserting a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream that assumes all memory accesses have drained from the multithreaded processor.
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Abstract
A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a functional unit within the multithreaded processor is configured in accordance with the multi-bit output of the state machine.
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Citations
33 Claims
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1. A method including:
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maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status of an associated thread of multiple threads being executed with a multithreaded processor;
detecting a change of status for a first thread within the multithreaded processor; and
responsive to the change of status for the first thread within the multithreaded processor, configuring a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine, wherein the configuring of the functional unit within the multithreaded processor includes inserting a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream that assumes all memory accesses have drained from the multithreaded processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. Apparatus including:
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a state machine to provide a multi-bit output, each bit of the multi-output indicating a respective status of an associated thread of multiple threads being executed within a multithreaded processor, and to detect a change of status for a first thread within the multithreaded processor; and
configuration logic to configure a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine; and
a microcode sequencer to introduce a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream to ensure that all memory accesses drain from the multithreaded processor. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. Apparatus comprising:
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first means for providing a multi-bit output, each bit of the multi-output indicating a respective status of an associated thread of multiple threads being executed within a multithreaded processor, and to detect a change of status for a first thread within the multithreaded processor; and
second means for configuring a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine, wherein the configuring of the functional unit within the multithreaded processor includes inserting a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream that assumes all memory accesses have drained from the multithreaded processor.
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33. A machine-readable medium including a sequence of instructions that, when executed by a machine, cause the machine to:
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maintain a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status of an associated thread of multiple threads being executed with a multithreaded processor;
detect a change of status for a first thread within the multithreaded processor; and
configure a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine, wherein the configuring of the functional unit within the multithreaded processor includes inserting a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream that assumes all memory accesses have drained from the multithreaded processor.
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Specification