Dynamic voltage control method and apparatus

• US 6,889,331 B2
• Filed: 08/29/2002
• Issued: 05/03/2005
• Est. Priority Date: 08/29/2001
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Soerensen, Joern, Allen, Michael, Birk, Palle
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/231,446
• Publication Number:
  US 20030071657A1
• Time in Patent Office: 978 Days
• Field of Search: 713/322, 713/500, 713/501, 713/600, 713/601, 713/320, 327/156, 327/159
• US Class Current: 713/320
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2213/3814 Wireless link with a computer system port
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H04W 88/06 : adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate
• CPC Class Codes: Y02D 30/70 : in wireless communication networks
• CPC Class Codes: Y10S 331/02 : Phase locked loop having lock indicating or detecting means

Abstract

A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

Claims

1. In a system including at least one processor having at least one clock signal capable of operating at a plurality of frequencies, a method of dynamic power control comprising acts of:

determining a clock frequency requirement of the at least one processor;

determining a voltage requirement to support the clock frequency requirement;

operating the at least one clock signal according to the clock frequency requirement; and

providing a voltage to supply the at least one processor according to the voltage requirement;

wherein the act of determining the voltage requirement includes an act of determining a maximum minimum clock frequency of the clock frequency requirement.

2. The method of claim 1, further comprising an act of determining a sign of a voltage difference between a current voltage supplied to the at least one processor and a voltage according to the voltage requirement.

3. The method of claim 2, wherein the act of providing the voltage to supply the at least one processor according to the voltage requirement is enacted before the act of operating the at least one clock signal according to the clock frequency requirement when the sign of the voltage difference is positive.

4. The method of claim 2, wherein the act of operating the at least one clock signal according to the clock frequency requirement is enacted before the act of providing the voltage to supply the at least one processor according to the voltage requirement when the sign of the voltage difference is negative.

5. The method of claim 1, wherein the at least one processor has a plurality of clock domains, each clock domain providing a clock signal at a plurality of frequencies to a plurality of components of the at least one processor;

and

wherein the act of determining the clock frequency requirement includes determining the minimum clock frequency required in each of the plurality of clock domains.

6. The method of claim 5, further comprising an act of comparing the minimum clock frequency required in each of the plurality of clock domains.

7. The method of claim 6, wherein the act of comparing includes comparing the minimum clock frequency required in each of the plurality of clock domains to determine a maximum minimum clock frequency required by the plurality of clock domains.

8. The method of claim 7, wherein the act of determining the voltage requirement includes determining the voltage requirement from the maximum minimum clock frequency.

9. The method of claim 1, wherein the at least one processor has a plurality of clock domains, each clock domain providing a clock signal to a plurality of components of the processor, each clock signal having at least one associated frequency;

and

wherein determining the clock frequency requirement includes determining whether each of the plurality of clock domains is required to be enabled.

10. The method of claim 9, wherein the act of determining the voltage requirement includes an act of determining the voltage requirement based on the at least one associated frequency of the clock domains that are required to be enabled.

11. A processor including at least one clock signal operating at a plurality of frequencies, the processor comprising:

one or more components receiving the at least one clock signal; and

a controller coupled to at least one of the components to identify a clock frequency requirement of the processor, the controller adapted to determine a voltage requirement based on the clock frequency requirement of the processor and to sequence a transition to a power state defined by the clock frequency requirement and the voltage requirement;

wherein the controller is coupled to at least one component by a plurality of registers, the plurality of registers storing information indicating the clock frequency requirement of the processor.

12. The processor of claim 11, wherein the controller further comprises a comparator coupled to the plurality of registers, the comparator configured to determine the voltage requirement based on the information stored in the plurality of registers.

13. The processor of claim 12, wherein the processor includes a plurality of clock signals, operating at a plurality of frequencies, and provided to the one or more clocked components.

14. The processor of claim 13, wherein the plurality of registers store values corresponding to the clock frequency requirement of each of the plurality of clock signals.

15. The processor of claim 14, wherein the comparator determines the maximum value stored in the plurality of registers to determined the clock frequency requirement.

16. The processor of claim 12, wherein the controller further comprises a memory to a plurality of voltage values.

17. The processor of claim 16, wherein the comparator maps the information stored in the plurality of registers to a location in memory storing a voltage value sufficient to support the clock frequency requirement of the processor.

18. The processor of claim 17, wherein the controller includes a finite state machine to sequence a transition to the power state defined by the clock frequency requirement and voltage requirement.

19. The processor of claim 18, wherein the finite state machine receives the voltage value obtained from the memory and determines a sign of a difference between a current voltage level being supplied to the processor and the obtained voltage value.

20. The processor of claim 19, wherein the finite state machine transitions the processor to operate with the obtained voltage value and then transitions the processor to operate with the clock frequency requirement when the sign of the difference is positive.

21. The processor of claim 19, wherein the finite state machine transitions the processor to operate with the clock frequency requirement and then transitions the processor to operate with the obtained voltage value when the sign of the difference is negative.

22. The processor of claim 11, wherein the at least one clock signal includes a plurality of clock signals provided to the one or more clocked components includes a plurality of clocked components.

23. The processor of claim 22, wherein the plurality of registers store a frequency value for each of the plurality of clock signals required by each of the plurality of clocked components.

24. The processor of claim 22, wherein the plurality of registers store a binary value to indicate whether each of the plurality of clocked components requires each of the plurality of clock signals.

25. A controller to dynamically control the power to a processor having a plurality of clock signals, the controller comprising:

a plurality of registers to store information indicating a clock frequency requirement of the processor;

a comparator coupled to the plurality of registers, the comparator configured to determine a voltage requirement based on the information stored in the plurality of registers; and

a sequencer coupled to the comparator and configured to transition the processor to a power state defined by the clock frequency requirement and the voltage requirement.

26. The controller of claim 25, wherein the plurality of registers store a plurality of frequency values required by a plurality of components of the processor.

27. The controller of claim 25, wherein each of the plurality of registers contain a bit for each of the plurality of clock signals provided to the processor, the bit indicating whether the corresponding clock signal is required to be enabled.

28. The controller of claim 26, wherein the comparator includes a memory to store a plurality of voltage values and wherein the comparator is configured to map the plurality of frequency values stored in the plurality of registers to a location in the memory storing a voltage value sufficient to support the clock frequency requirement indicated by the plurality of frequency values.

29. The controller of claim 26, wherein the comparator includes a programmable logic array, the comparator adapted to map the plurality of frequency values stored in the plurality of registers to an input to the programmable logic array, the programmable logic array programmed to provide an output to the sequencer indicative of a voltage value required to support the clock frequency requirement.

30. The controller of claim 25, wherein the sequencer is a finite state machine.

31. The controller of claim 25, in combination with the processor, the processor further including a plurality of components.

32. The combination of claim 31, wherein each of the plurality of components indicates via a respective one of the plurality of registers a clock frequency requirement of the component.

33. The combination of claim 25, wherein the plurality of registers include a bit corresponding to each of the plurality of clock signals.

34. The combination of claim 33, wherein each of the plurality of components is associated with at least one of the plurality of registers and each of the plurality of components indicate, via the bit corresponding to each of the plurality of clocks signals, whether the respective clock signal is required.

35. A device comprising:

at least one processor having a plurality of components operating with a plurality of clock signals;

a power supply adapted to provide a variable level voltage to the at least one processor;

a clock controller adapted to control a frequency of the plurality of clock signals; and

a dynamic power controller, connected to the power supply and the clock controller, adapted to monitor the at least one processor to determine a clock frequency requirement of the at least one processor and to determine a voltage requirement based on the clock frequency requirement, and configured to transition the power supply and the clock controller to a power state defined by the clock frequency requirement and the voltage requirement.

36. The low power device of claim 35, wherein the plurality of clock signals includes a system clock signal.

37. The low power device of claim 36, wherein the clock controller includes a phase locked loop (PLL) frequency multiplier to provide a high frequency clock signal synchronized to the system clock signal.

38. The low power device of claim 37, wherein the plurality of clock signals are derived from the system clock signal and the high frequency clock signal.