Device for sealing and cooling multi-chip modules

• US 6,890,799 B2
• Filed: 01/07/2003
• Issued: 05/10/2005
• Est. Priority Date: 08/05/1999
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Koyano, Koichi, Kasai, Kenichi, Netsu, Toshitada, Uda, Takayuki, Daikoku, Takahiro
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US10/338,485
• Publication Number:
  US 20030103333A1
• Time in Patent Office: 854 Days
• Field of Search: 257/706, 257/707, 257/712, 257/713, 257/714, 257/718, 257/720, 257/722, 257/678, 257/704, 257/717, 257/723, 257/724, 257/730, 438/106, 438/121, 438/122, 361/679, 361/688, 361/689, 361/704, 361/702, 361/703, 361709-711, 361/718, 361/719
• US Class Current: 438/122
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/1626 Cap-in-cap assemblies

Abstract

According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.

Claims

1. A method for sealing multi-chip modules, said multi-chip modules comprising a circuit substrate having a plurality of semiconductor devices mounted thereon, and a frame, said frame fixed to said circuit substrate and formed from a material having a thermal expansion coefficient consistent with a thermal expansion coefficient of said circuit substrate, said method comprising:

forming onto a first surface of a sealing top plate a cooling flow path having openings through which cooling fluid may flow;

bonding a second surface of said sealing top plate to a back surface of said semiconductor devices;

joining an edge of said sealing plate to said frame to form a first seal;

covering said cooling flow path with a cooling flow path cover;

interposing a sealing material between said edge of said sealing top plate and said cooling flow path cover to form a second seal; and

tightening together said cooling flow path cover, said sealing material, said sealing top plate and said frame.

2. A method for sealing multi-chip modules as described in claim 1 wherein:

said bonding a second surface of said sealing top plate to a back surface of said semiconductor devices further comprises;

soldering said back surface of said semiconductor devices to said second surface of said sealing top plate.

3. A method for sealing multi-chip modules as described in claim 1 wherein:

said sealing top plate is formed from an aluminum nitride ceramic having high thermal conductivity; and

said cooling flow path cover is metallic.

4. A method for sealing multi-chip modules as described in claim 1 further comprising:

forming an offset on said back surface of said semiconductor device; and

soldering a higher surface of said offset to said sealing top plate.

5. A method for sealing multi-chip modules as described in claim 4 wherein said offset is at substantially 500 micrometers measured from said back surface of said semiconductor device.

6. A method for sealing multi-chip modules as described in claim 1 wherein said semiconductor devices comprise micro-packages containing LSI chips.

7. A method for sealing multi-chip modules as described in claim 1 wherein said tightening further comprises tightening at least one of a plurality of bolts.

8. A method for sealing multi-chip modules as described in claim 1 wherein said sealing material comprises an o-ring.

9. A method for sealing multi-chip modules as described in claim 1 wherein said first seal comprises a butt-joint.

10. A method for sealing multi-chip modules as described in claim 1 further comprising injecting nitrogen gas into an air tight area formed by said second surface of said sealing top plate, said frame, a first surface of said circuit substrate, and said first seal.