Semiconductor packages and methods for making the same

• US 6,891,108 B2
• Filed: 10/04/2001
• Issued: 05/10/2005
• Est. Priority Date: 06/07/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jiang, Tongbi, Street, Bret, Prindiville, Casey
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): NORRIS, JEREMY C
• Application Number:
  US09/971,985
• Publication Number:
  US 20020020902A1
• Time in Patent Office: 1,314 Days
• Field of Search: 174/260, 174/255, 257/723, 257773-776, 438/108, 361/783
• US Class Current: 174/255
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

Semiconductor package support elements including cover members attached to one or more reject die sites. Also, methods for making the support elements and for making semiconductor packages using the same. Reject die sites on defective substrates of a support element are covered prior to the encapsulation process using a cover member. The cover member comprises, for example, pressure-sensitive or temperature-activated tape, reject dies, or the like. The support elements and methods of the present invention virtually eliminate bleeding or flashing during encapsulation due to the presence of reject die sites. The support elements and methods of the present invention further ensure that functional dice are not sacrificed by being attached to reject die sites, thereby decreasing manufacturing costs while increasing yield of functional semiconductor packages.

Claims

1. A support element for a semiconductor package, the support element comprising:

(a) a first surface having a plurality of conductors;

(b) a second surface having a plurality of die attach areas, wherein at least one of the die attach areas comprises a defective die attach area;

(c) the die attach areas including wire bond slots extending from the first surface to the second surface of the support element so as to form openings therethrough; and

(d) a cover member attached to the at least one defective die attach area so as to cover at least a portion of the wire bond slot, wherein the cover member does not comprise a functional die.

2. The support element of claim 1, wherein the cover member comprises self-adhesive tape.

3. The support element of claim 1, wherein the cover member comprises a defective die.

4. The support element of claim 1, wherein the cover member covers from about 80% to about 90% of the wire bond slot.

5. The support element of claim 1, wherein the cover member covers at least 70% of an opening formed by the wire bond slot.

6. A support element for a semiconductor package, the support element comprising:

(a) a first surface having a plurality of conductors;

(b) a second surface having a plurality of die attach areas, wherein at least one of the die attach areas comprises a defective die attach area;

(c) the die attach areas including wire bond slots extending from the first surface to the second surface of the support element so as to form openings therethrough; and

(d) a cover member attached to the at least one defective die attach area so as to cover enough of the opening formed by the wire bond slot so as to substantially eliminate bleeding when the support element in encapsulated, wherein the cover member does not comprise a functional die.

7. The support element of claim 6, wherein the cover element does not cover enough of the opening so as to cause a negative pressure zone at the wire bond slot when the support element is encapsulated with a liquid plastic.

8. The support element of claim 6, wherein the cover member comprises heat-sensitive tape covering a majority of an opening formed by a wire bond slot.

9. A support element for a semiconductor package, the support element comprising:

(a) a first surface having a plurality of conductors;

(b) a second surface having a plurality of die attach areas, wherein at least one of the die attach areas comprises a defective die attach area;

(c) the die attach areas including wire bond slots extending from the first surface to the second surface of the support element so as to form openings therethrough; and

(d) a defective die attached to the at least one defective die attach area so as to cover at least a portion of the wire bond slot.

10. The support element of claim 9, wherein the defective die covers from about 80% to about 90% of an opening formed by a wire bond slot.

11. A support element for a semiconductor package, the support element comprising:

(a) a first surface having a plurality of conductors;

(b) a second surface having a plurality of die attach areas, wherein at least one of the die attach areas comprises a defective die attach area;

(c) the die attach areas including wire bond slots extending from the first surface to the second surface of the support element so as to form openings therethrough; and

(d) tape attached to the at least one defective die attach area so as to cover at least a portion of the wire bond slot.

12. A substrate of a support element, the substrate comprising:

(a) a first surface having a pattern of conductors;

(b) a second surface having a die attach area with defective electrical circuitry;

(c) a wire bond slot forming an opening through the substrate extending from the first surface to the second surface; and

(d) a defective die attached to the substrate on the second surface so as to cover at least a portion of the wire bond slot.

13. A support element for a semiconductor package, the support element comprising:

(a) a first surface having a plurality of conductors;

(b) a second surface having a plurality of die attach sites, wherein a first die attach site is defective and a second die attach site is functional;

(c) a plurality of integrally connected substrates formed by the first and second surfaces; and

(d) the substrate including wire bond slots extending from the first surface to the second surface of the support element so as to form openings therethrough, wherein there is at least one opening formed at the first and the second die attach sites;

(e) a cover member attached to the first die attach site so as to cover from about 70% to about 100% of the opening.