Micro power micro-sized CMOS active pixel

• US 6,891,145 B2
• Filed: 05/14/2002
• Issued: 05/10/2005
• Est. Priority Date: 10/14/1998
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Bock, Nikolai E.
• Primary Examiner(s): Le, Que T.
• Application Number:
  US10/146,667
• Publication Number:
  US 20020190192A1
• Time in Patent Office: 1,092 Days
• Field of Search: 250/214.R, 250/214.1, 250/208.1, 348/297, 348/304, 348/308, 257/290, 257/291, 257/440
• US Class Current: 250/214.00R
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/573 the logarithmic type
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

Reduced size CMOS active pixel circuit uses special transistors with their gates and sources connected together. This transistor is placed at the top of the pixel.

Claims

1. A method of operating a pixel unit of an imaging device, said method comprising:

resetting a charge accumulation region with a reset pulse having a voltage greater than an operating voltage of said imaging device;

accumulating charge provided by a photoreceptor at said charge accumulation region; and

selectively outputting a signal based on the charge at said accumulation region produced by said photoreceptor.

2. The method of claim 1, wherein the reset pulse comprises an output voltage of a booster circuit.

3. The method of claim 1, further comprising applying said reset pulse to a gate and one of a source/drain region of a reset transistor, and resetting said charge accumulation region by a signal produced at the other of said source/drain region of said reset transistor.

4. The method of claim 1, wherein said selectively outputting comprises selectively applying a select signal to a gate and one of a source/drain terminal of a select transistor, the other of said source/drain terminal providing an operating voltage for an output transistor having a gate coupled to receive a signal from said charge accumulation region.

5. The method of claim 4, wherein said select signal has a voltage greater than said operating voltage of said imaging device.

6. An integrated circuit, comprising:

a charge accumulating region on said integrated circuit, said region receiving accumulated charge therein;

a photoreceptor, coupled to said charge accumulating region, for changing an amount of charge therein based on an applied image signal;

a reset transistor, having a drain and gate terminal coupled together, said reset transistor activating to provide a reset pulse to said charge accumulation region; and

a select transistor, having a drain and gate terminal coupled together, and coupled to selectively cause the production of an output signal based on the charges at said charge accumulation region.

7. The integrated circuit of claim 6, further comprising a source follower transistor, having a gate coupled to said charge accumulation region and one source/drain region coupled to said transistor and another source/drain region providing said output signal.

8. The integrated circuit of claim 6, wherein the reset pulse has a voltage greater than an operating voltage of the integrated circuit.

9. The integrated circuit of claim 6, wherein the select transistor receives a select signal at a gate and one of a source/drain terminal, the other of said source/drain terminal providing the operating voltage for an output transistor having a gate coupled to said charge accumulation region.

10. The integrated circuit of claim 9, wherein the select signal has a voltage greater than an operating voltage of the integrated circuit.