Base current reversal SRAM memory cell and method

• US 6,891,213 B1
• Filed: 07/23/2003
• Issued: 05/10/2005
• Est. Priority Date: 03/16/1999
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/626,777
• Time in Patent Office: 657 Days
• Field of Search: 257/288, 257/289, 257/296
• US Class Current: 257/296
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Claims

1. A memory cell, comprising:

a column of epitaxial layers having a first dimension along a first axis and a second dimension along a second axis perpendicular to the first axis;

an oxide formed under the columns of epitaxial layers;

a storage device formed in a lower layer of the epitaxial layers of the columns; and

an access element formed on a surface of the column, the access element having a dimension in the first direction less than the first dimension of the column.

2. The memory cell of claim 1 wherein the storage device comprises a bipolar junction transistor.

3. The memory cell of claim 1 wherein the access element comprises a vertical p-channel MOS transistor.

4. The memory cell of claim 1 wherein the first dimension of the column corresponds to a feature size of the memory cell.

5. The memory cell of claim 1 wherein the dimension of the vertical access element in the first direction is less than half the first dimension of the column.

6. The memory cell of claim 1 wherein the storage device comprises a bipolar junction transistor and the access element comprises a vertical p-channel MOS transistor having a source formed in the same epitaxial layer in which the bipolar junction transistor is formed.

7. A memory cell, comprising:

a column of epitaxial layers perpendicular to a substrate surface, the column having a lower epitaxial layer on which the other epitaxial layers are formed, the column further having a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction;

a storage device formed in the lower epitaxial layer of the column; and

a vertical access element formed on a surface of the column, the vertical access element having a dimension in the first direction less than the first dimension of the column.

8. The memory cell of claim 7 wherein the storage device comprises a bipolar junction transistor.

9. The memory cell of claim 7 wherein the vertical access element comprises a vertical p-channel MOS transistor.

10. The memory cell of claim 7 wherein the first dimension of the column corresponds to a feature size of the memory cell.

11. The memory cell of claim 7 wherein the dimension of the vertical access element in the first direction is less than half the first dimension of the column.

12. The memory cell of claim 7 wherein the storage device comprises a bipolar junction transistor and the vertical access element comprises a vertical p-channel MOS transistor having a source formed in the same epitaxial layer in which the bipolar junction transistor is formed.

13. An array of memory cells, comprising:

a plurality of columns of epitaxial layers formed on a substrate surface, the columns of epitaxial layers having a first dimension along a first axis and second dimension along a second axis perpendicular to the first axis;

a plurality of trenches separating the plurality of columns, each trench having a width in the direction of the first axis;

a plurality of storage devices, each storage device formed in a lower layer of the epitaxial layers of the columns; and

a plurality of access elements, each access element formed within a trench and on a surface of a respective column and having a dimension in the direction of the first axis that is less than the first dimension of the columns.

14. The array of memory cells of claim 13 wherein a first access element for a first memory cell and a second access element for a second memory cell are formed in the same trench.

15. The array of memory cells of claim 13 wherein each of the storage devices comprises a bipolar junction transistor.

16. The array of memory cells of claim 13 wherein each of the vertical access elements comprises a vertical p-channel MOS transistor.

17. The array of memory cells of claim 13 wherein the first dimension of each column corresponds to a feature size of the memory cells.

18. The array of memory cells of claim 13 wherein each of the storage devices comprises a bipolar junction transistor and each of the vertical access elements comprises a vertical p-channel MOS transistor having a source formed in the same epitaxial layer in which the bipolar junction transistor is formed.