Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit

• US 6,891,258 B1
• Filed: 12/06/2002
• Issued: 05/10/2005
• Est. Priority Date: 12/06/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Alexander, Mark A., Conn, Robert O., Carey, Steven J.
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US10/313,482
• Time in Patent Office: 886 Days
• Field of Search: 257/738, 257/774, 257/777, 257/780, 257/737, 257/713, 257/722, 257/784, 257/690, 257/691, 257/698, 257/699
• US Class Current: 257/678
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19103 interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 2201/10515 Stacked components
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array

Abstract

Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

Claims

1. A structure, comprising:

a packaged integrated circuit (IC) having a plurality of package pins disposed according to a first pattern;

a printed circuit board (PCB) having a plurality of PCB lands disposed thereon according to the first pattern;

a body having upper and lower surfaces, the body comprising a plurality of alternating conductive layers and dielectric layers, the outermost layers comprising dielectric layers;

a plurality of lands disposed upon the upper surface of the body according to the first pattern and directly coupled to the package pins;

a plurality of terminals disposed upon the lower surface of the body according to the first pattern and directly coupled to the PCB lands; and

a plurality of vias through the body and orthogonal to the upper and lower surfaces, each via providing an electrically conductive path between an associated land and an associated terminal, wherein;

each conductive layer in the body comprises one or more electrically insulating keepouts disposed around at least a subset of the vias.

2. The structure of claim 1, wherein a subset of the vias are not in electrical contact with any of the conductive layers.

3. The structure of claim 2, wherein at least some of the subset of vias are manufactured using a resistive material.

4. The structure of claim 1, wherein the vias comprise soldering material added to the structure after the manufacture of the body.

5. The structure of claim 1, wherein the dielectric layers comprise at least one of a group of materials including:

a ceramic material, an organic material, and a non-ceramic inorganic material.

6. The structure of claim 1, wherein each of the dielectric layers comprises at least one of a group of materials including:

a ceramic material, an organic material, and a non-ceramic inorganic material.

7. The structure of claim 5, wherein at least two of the dielectric layers are comprised of different dielectric materials.

8. The structure of claim 1, wherein at least one of the dielectric layers comprises a composite material including epoxy.

9. The structure of claim 1, wherein the body comprises a single unbroken device.

10. The structure of claim 1, wherein the body comprises an array of tiles coupled together using an elastomer material.

11. The structure of claim 1, wherein the terminals are balls similar to those used in a ball grid array (BGA) package.

12. The structure of claim 1, wherein at least one conductive layer is divided into two or more areas not having a direct current connection with each other.

13. The structure of claim 1, further comprising a plurality of conductive traces disposed between two of the dielectric layers and providing electrically conductive paths between pairs of the lands and the terminals, wherein the land and the terminal of each pair are positioned in different locations on the body.

14. The structure of claim 1, further comprising a plurality of conductive traces disposed between two of the dielectric layers and providing electrically conductive paths between pairs of the lands.

15. The structure of claim 1, further comprising a plurality of conductive traces disposed between two of the dielectric layers and providing electrically conductive paths between pairs of the terminals.

16. The structure of claim 1, wherein the conductive layers include at least two ground layers and at least one power layer, and the conductive layers are disposed in alternate ground and power layers.

17. The structure of claim 1, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling at least one of the lands to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling at least one of the terminals to the at least one electrically conductive trace.

18. The structure of claim 1, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling a first one of the lands to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling a second one of the lands to the at least one electrically conductive trace.

19. The structure of claim 1, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling a first one of the terminals to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling a second one of the terminals to the at least one electrically conductive trace.

20. A system, comprising:

a packaged integrated circuit (IC) having a plurality of package pins;

a printed circuit board (PCB) having a plurality of lands disposed thereon; and

a first capacitive interposer structure physically located between the PCB and the packaged IC and directly coupled therebetween, the first capacitive interposer structure comprising;

a body having upper and lower surfaces, the body comprising a plurality of alternating conductive layers and dielectric layers, the outermost layers comprising dielectric layers;

a plurality of lands disposed upon the upper surface of the body, each land being coupled to one of the package pins of the packaged IC;

a plurality of terminals disposed upon the lower surface of the body, each terminal being coupled to one of the lands of the PCB; and

a plurality of vias through the body and orthogonal to the upper and lower surfaces, each via providing an electrically conductive path between an associated land and an associated terminal, wherein;

each conductive layer in the body comprises one or more electrically insulating keepouts disposed around at least a subset of the vias.

21. The system of claim 20, wherein the lands on the PCB are disposed to correspond to the locations of the package pins of the packaged IC.

22. The system of claim 20, wherein:

the package pins of the packaged IC include at least one ground pin and at least one power pin;

one or more conductive layers are coupled to the ground pin of the packaged IC; and

one or more conductive layers are coupled to the power pin of the packaged IC.

23. The system of claim 22, wherein:

the package pins of the packaged IC further include at least an additional power pin not having a direct current connection to the at least one power pin; and

one or more conductive layers are coupled to the additional power pin of the packaged IC.

24. The system of claim 20, wherein the terminals are balls similar to those used in a ball grid array (BGA) package.

25. The system of claim 20 wherein:

the packaged IC comprises a ball grid array (BGA) package wherein each package pin is a ball; and

each ball of the BGA package is soldered to a corresponding land of the first capacitive interposer structure.

26. The system of claim 20 wherein:

the package pins of the packaged IC include a plurality of signal pins;

the vias include a plurality of signal vias coupled to the plurality of signal pins; and

the signal vias are not in electrical contact with any of the conductive layers.

27. The system of claim 26, wherein at least one of the signal vias is manufactured using a resistive material.

28. The system of claim 20, wherein the first capacitive interposer structure has a comparable footprint to the packaged IC.

29. The system of claim 20, wherein the first capacitive interposer structure has a larger footprint than the packaged IC.

30. The system of claim 20, wherein:

the first capacitive interposer structure has a smaller footprint than the packaged IC and is coupled to fewer than all of the package pins; and

the structure further comprises one or more additional capacitive interposer structures coupled to the remaining package pins of the IC and further coupled to the lands of the PCB.

31. The system of claim 30 wherein the combined footprints of the first capacitive interposer structure and the additional capacitive interposer structures are about the same as the footprint of the packaged IC.

32. The system of claim 30, wherein the first capacitive interposer structure and the additional capacitive interposer structures are fastened together using an elastomer material.

33. The system of claim 20, wherein at least one of the conductive layers is divided into first and second areas not having a direct current connection with each other.

34. The system of claim 33, wherein:

the package pins of the packaged IC include at least an additional power pin not having a direct current connection to the at least one power pin;

the first area is coupled to the at least one power pin; and

the second area is coupled to the additional power pin.

35. The system of claim 20, wherein the body of the capacitive interposer structure further comprises a plurality of conductive traces disposed between two of the dielectric layers and providing electrically conductive paths between pairs of the lands and the terminals, wherein the land and the terminal of each pair are positioned in different locations on the body.

36. The system of claim 20, wherein the body of the capacitive interposer structure further comprises an additional conductive layer comprising a plurality of conductive traces disposed between two of the dielectric layers and providing electrically conductive paths between pairs of the lands.

37. The system of claim 20, wherein the body of the capacitive interposer structure further comprises a plurality of conductive traces disposed between two of the dielectric layers and providing electrically conductive paths between pairs of the terminals.

38. The system of claim 20, wherein at least two of the dielectric layers are comprised of different dielectric materials.

39. The system of claim 20, wherein the conductive layers include at least two ground layers and at least one power layer, and the conductive layers are disposed in alternate ground and power layers.

40. The system of claim 20, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling at least one of the lands to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling at least one of the terminals to the at least one electrically conductive trace.

41. The system of claim 20, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling a first one of the lands to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling a second one of the lands to the at least one electrically conductive trace.

42. The system of claim 20, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling a first one of the terminals to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling a second one of the terminals to the at least one electrically conductive trace.

43. An interposer, comprising:

a plurality of alternate planar conductive layers and planar dielectric layers, the dielectric layers including first and second outermost layers;

a plurality of lands disposed on an outer surface of the first dielectric layer in a pattern;

a plurality of terminals disposed on an outer surface of the second dielectric layer in the pattern of the lands;

a plurality of vias formed through the planar conductive and dielectric layers and orthogonal to the outer surfaces, each via providing an electrically conductive path between a land and a terminal at a corresponding position in the pattern; and

a plurality of electrically insulative structures, each structure surrounding a via in one of the planar conductive layers and surrounded by electrically conductive material in the planar conductive layer.

44. The interposer of claim 43, wherein a at least one of the vias is insulated from electrical contact with all of the planar conductive layers.

45. The interposer of claim 43, wherein the dielectric layers comprise at least one of a group of materials including:

a ceramic material, an organic material, and a non-ceramic inorganic material.

46. The interposer of claim 45, wherein at least two of the dielectric layers are comprised of different dielectric materials.

47. The interposer of claim 43, wherein each of the dielectric layers comprises at least one of a group of materials including:

a ceramic material, an organic material, and a non-ceramic inorganic material.

48. The interposer of claim 43, wherein at least one of the dielectric layers comprises a composite material including epoxy.

49. The interposer of claim 43, wherein the planar conductive layers include at least two ground layers and at least one power layer, and the conductive layers are disposed in alternate ground and power layers.

50. The interposer of claim 43, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling at least one of the lands to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling at least one of the terminals to the at least one electrically conductive trace.

51. The interposer of claim 43, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling a first one of the lands to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling a second one of the lands to the at least one electrically conductive trace.

52. The interposer of claim 43, further comprising:

at least one electrically conductive trace disposed between two of the dielectric layers;

a first partial via extending from and electrically coupling a first one of the terminals to the at least one electrically conductive trace; and

a second partial via extending from and electrically coupling a second one of the terminals to the at least one electrically conductive trace.

53. An interposer, comprising:

an array of tiles coupled together using an elastomer material, wherein each tile includes,

a plurality of alternate planar conductive layers and planar dielectric layers, the dielectric layers including first and second outermost layers;

a plurality of lands disposed on an outer surface of the first dielectric layer in a pattern;

a plurality of terminals disposed on an outer surface of the second dielectric layer in the pattern of the lands;

of vias formed through the planar conductive and dielectric layers and orthogonal to the outer surfaces, each via providing an electrically conductive path between a land and a terminal at a corresponding position in the pattern; and

a plurality of electrically insulative structures, each structure surrounding a via in one planar conductive layers and surrounded by electrically conductive material in the planar conductive layer.