Circuit analysis using electric field-induced effects

• US 6,891,390 B1
• Filed: 02/28/2002
• Issued: 05/10/2005
• Est. Priority Date: 02/28/2002
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Goruganthu, Rama R., Bruce, Michael R.
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Geyer, Scott B.
• Application Number:
  US10/086,505
• Time in Patent Office: 1,167 Days
• Field of Search: 438/5, 438/10, 438/11, 438/12, 438/14, 438/17, 438/18, 324/765, 324/750, 731/04, 731/05, 250/306
• US Class Current: 324/754.27
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: Y10S 977/854 Semiconductor sample

Abstract

Circuitry within a semiconductor die is analyzed by applying an electric field without necessarily directly accessing the circuitry. According to an example embodiment of the present invention, an electric field is applied to a semiconductor die and used to stimulate circuitry therein. A response of the die to the electric field is detected and used to detect an electrical characteristic of the die. This is particularly useful in applications where it is desired to direct stimulation to the die on a nanoscale level, such as when using a fine probe tip (e.g., a scanning probe microscope tip) to apply the electric field. In this manner, the response of the die can be mapped to circuitry within a few nanometers of the probe tip.

Claims

1. A method for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the method comprising:

applying an electric field to the die via a voltage-application tool, separate from the die and using the applied electric field to stimulate circuitry in the die including applying an electric field to circuitry via a die passivation layer in a conventionally packaged semiconductor die;

detecting a response of the die to the applied electric field; and

using the response to detect an electrical characteristic from the die.

2. A method for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the method comprising:

applying an electric field to the die via a voltage-application tool, separate from the die and using the applied electric field to stimulate circuitry in the die including applying an electric field to circuitry via a backside of a flip-chip packaged die;

detecting a response of the die to the applied electric field; and

using the response to detect an electrical characteristic from the die.

3. The method of claim 2, wherein applying an electric field to circuitry via a backside of a flip-chip packaged die includes applying an electric field via a thinned backside of the flip-chip packaged die.

4. The method of claim 3, further comprising thinning the backside of the flip-chip packaged die and thereby forming the thinned backside.

5. A method for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the method comprising:

applying an electric field to the die via a voltage-application tool, separate from the die and using the applied electric field to stimulate circuitry in the die including applying an electric field to circuitry via an insulator portion of silicon-on-insulator structure in a die;

detecting a response of the die to the applied electric field; and

using the response to detect an electrical characteristic from the die.

6. The method of claim 5, further comprising thinning a portion of the die and exposing the insulator portion of the silicon-on-insulator structure, wherein applying an electric field to circuitry via the insulator portion includes applying the electric field via the exposed insulator portion.

7. A method for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the method comprising:

applying an electric field to the die via a voltage-application tool, separate from the die and using the applied electric field to stimulate circuitry in the die using at least one of;

a scanning probe microscope, an atomic force microscope and a capacitance probe microscope;

detecting a response of the die to the applied electric field; and

using the response to detect an electrical characteristic from the die.

8. A method for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the method comprising:

applying an electric field to the die via a voltage-application tool, separate from the die and using the applied electric field to stimulate circuitry in the die including positioning a probe tip over a portion of circuitry in the die and applying a voltage to the probe tip;

detecting a response of the die to the applied electric field; and

using the response to detect an electrical characteristic from the die.

9. The method of claim 8, wherein applying a voltage to the probe tip includes applying a voltage that varies over time to the probe tip.

10. The method of claim 8, wherein detecting a response of the die to the applied electric field includes detecting a position of the probe tip over the die and mapping the detected response to circuitry in the die below the probe tip.

11. The method of claim 8, wherein positioning the probe tip includes scanning the probe tip over the die.

12. The method of claim 11, wherein detecting a response of the die includes detecting responses from a plurality of circuits in the die as the probe tip is scanned over the circuits.

13. The method of claim 8, wherein applying a voltage to the probe tip includes applying a periodic voltage that is relative to a voltage at a reference node in the die.

14. The method of claim 8, wherein positioning a probe tip includes positioning a probe tip having a radius that is sufficiently small to stimulate a selected node in the die without stimulating circuitry adjacent to the selected node.

15. The method of claim 8, wherein positioning a tip over a portion of circuitry in the die includes positioning the tip using nanometer-level resolution.

16. A method for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the method comprising:

applying an electric field to the die via a voltage-application tool, separate from the die and using the applied electric field to stimulate circuitry in the die including applying the electric field to circuitry via an opaque layer in the die, the circuitry being buried in the die below the opaque layer;

detecting a response of the die to the applied electric field; and

using the response to detect an electrical characteristic from the die.

17. A method for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the method comprising:

applying an electric field to the die via a voltage-application tool, separate from the die and using the applied electric field to stimulate circuitry in the die;

detecting a response of the die to the applied electric field;

using the response to detect an electrical characteristic from the die; and

using the detected electrical characteristic to provide a modified die design and manufacturing a semiconductor device using the modified die design.

18. A semiconductor device manufactured using the modified die design of claim 17.

19. A system for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the system comprising:

means, separate from the die and adapted for applying an electric field to the die and using the applied electric field to stimulate circuitry in the die;

means for detecting a response of die to the applied electric field; and

means for using the response to detect an electrical characteristic of the die.

20. A system for analyzing a semiconductor die having circuitry in a circuit side opposite a back side, the system comprising:

a probe tip arrangement, separate from the die and adapted for applying an electric field to the die for stimulating circuitry in the die;

electrical detection circuitry adapted for detecting a response of die to the applied electric field; and

a computer arrangement adapted for using the response to detect an electrical characteristics of the die.

21. The system of claim 20;

wherein the probe tip is sufficiently small to apply an electric field to stimulate a selected circuit node in the die without stimulating surrounding circuitry in the die.