Skewed falling logic device for rapidly propagating a falling edge of an output signal

• US 6,891,398 B2
• Filed: 01/03/2003
• Issued: 05/10/2005
• Est. Priority Date: 08/03/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Porter, John D., Weber, Larren G., Gans, Dean D.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/336,357
• Publication Number:
  US 20030098717A1
• Time in Patent Office: 858 Days
• Field of Search: 326/82, 326/83, 326/30, 326/98, 326/114, 326/119, 327/203
• US Class Current: 326/82
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

Claims

1. A skewed NOR falling logic device for rapidly propagating a falling edge of an output signal, comprising:

a fast NOR gate falling having a large n/p channel width ratio for receiving a first input signal and a second input signal and rapidly propagating a falling edge of said output signal in response to a rising edge on either of said first input signal or said second input signal;

a pull-up reset network connected in parallel with said fast NOR gate falling for resetting said output signal; and

a feedback delay circuit connected in parallel with said pull-up reset network for propagating said output signal to an input of said pull-up reset network.

2. The skewed NOR falling logic device of claim 1, wherein said large n/p channel width ratio ranges from about 5 to about 200.

3. The skewed NOR falling logic device of claim 1, wherein said pull-up reset network comprises:

combinational logic having a first input, a second input, a third input and an output; and

a big PMOS transistor having a wide p-channel at least 10 μ

m across, a gate node connected to said output of said combinational logic, a source node connected to a supply voltage and a drain node connected to said output signal.

4. The skewed NOR falling logic device of claim 3, wherein said combinational logic performs a logical OR function.

5. The skewed NOR falling logic device of claim 3, wherein said combinational logic comprises:

a 3-input NOR gate having said first input connected to said first input signal, having said second input connected to said second input signal and having said third input connected to an output of said feedback delay circuit; and

an inverter having an input connected to an output of said 3-input NOR gate and having an output driving said output of said combinational logic.

6. The skewed NOR falling logic device of claim 1, wherein said feedback delay circuit comprises four inverters connected in series.

7. A skewed NAND falling logic device for rapidly propagating a falling edge of an output signal, comprising:

a fast NAND gate falling having a large n/p channel width ratio for receiving both a first input signal and a second input signal and rapidly propagating a falling edge of said output signal in response to rising edges on both said first input signal and said second input signal;

a pull-up reset network connected in parallel with said fast NAND gate falling for resetting said output signal after said falling edge of said output signal has been propagated; and

a feedback delay circuit connected in parallel with said pull-up reset network for delaying and returning said output signal to an input of said pull-up reset network.

8. The skewed NAND falling logic device of claim 7, wherein said large n/p channel width ratio ranges from about 5 to about 200.

9. The skewed NAND falling logic device of claim 7, wherein said pull-up reset network comprises:

combinational logic having a plurality of inputs and an output;

a big PMOS transistor having a wide p-channel at least 10 μ

m across, a gate node connected to said output of said combinational logic, a source node connected to a supply voltage and a drain node connected to said output signal.

10. The skewed NAND falling logic device of claim 7, wherein said combinational logic performs a logical product of sums function.

11. The skewed NAND falling logic device of claim 9, wherein said combinational logic comprises:

a first NOR gate having a first input connected to said first input signal and a second input connected to an output of said feedback delay circuit;

a second NOR gate having a first input connected to said second input signal and a second input connected to said output of said feedback delay circuit; and

a third NOR gate having a first input connected to an output of said first NOR gate, a second input connected to an output of said second NOR gate and an output connected to said gate node of said big PMOS transistor.

12. The skewed NAND falling logic device of claim 7, wherein said feedback delay circuit comprises four inverters connected in series.